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Peter Anvin" Subject: [PATCH 3/5] [RESEND] x86: qspinlock-paravirt: fix mising-prototype warnings Date: Tue, 25 Jul 2023 15:48:35 +0200 Message-Id: <20230725134837.1534228-4-arnd@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230725134837.1534228-1-arnd@kernel.org> References: <20230725134837.1534228-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772402872093849092 X-GMAIL-MSGID: 1772402872093849092 From: Arnd Bergmann __pv_queued_spin_unlock_slowpath is defined in a header file as a global function, and designed to be called from an inline asm, but there is no prototype visible in the definition: kernel/locking/qspinlock_paravirt.h:493:1: error: no previous prototype for '__pv_queued_spin_unlock_slowpath' [-Werror=missing-prototypes] Add this to the x86 header that contains the inline asm calling it, and ensure this gets included before the definition, rather than after it. The native_pv_lock_init function in turn is only declared in SMP builds but can be left out in UP to avoid another warning: arch/x86/kernel/paravirt.c:76:13: error: no previous prototype for 'native_pv_lock_init' [-Werror=missing-prototypes] Signed-off-by: Arnd Bergmann --- arch/x86/include/asm/qspinlock_paravirt.h | 2 ++ arch/x86/kernel/paravirt.c | 2 ++ kernel/locking/qspinlock_paravirt.h | 20 ++++++++++---------- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/asm/qspinlock_paravirt.h index 42b17cf10b10e..85b6e3609cb92 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -4,6 +4,8 @@ #include +void __lockfunc __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked); + /* * For x86-64, PV_CALLEE_SAVE_REGS_THUNK() saves and restores 8 64-bit * registers. For i386, however, only 1 32-bit register needs to be saved diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 89842bb7ec9cc..64a6bba70d183 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -73,11 +73,13 @@ DEFINE_PARAVIRT_ASM(pv_native_read_cr2, "mov %cr2, %rax", .noinstr.text); DEFINE_STATIC_KEY_TRUE(virt_spin_lock_key); +#ifdef CONFIG_SMP void __init native_pv_lock_init(void) { if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) static_branch_disable(&virt_spin_lock_key); } +#endif unsigned int paravirt_patch(u8 type, void *insn_buff, unsigned long addr, unsigned int len) diff --git a/kernel/locking/qspinlock_paravirt.h b/kernel/locking/qspinlock_paravirt.h index 6afc249ce697d..6a0184e9c2348 100644 --- a/kernel/locking/qspinlock_paravirt.h +++ b/kernel/locking/qspinlock_paravirt.h @@ -485,6 +485,16 @@ pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL); } +/* + * Include the architecture specific callee-save thunk of the + * __pv_queued_spin_unlock(). This thunk is put together with + * __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock + * function close to each other sharing consecutive instruction cachelines. + * Alternatively, architecture specific version of __pv_queued_spin_unlock() + * can be defined. + */ +#include + /* * PV versions of the unlock fastpath and slowpath functions to be used * instead of queued_spin_unlock(). @@ -533,16 +543,6 @@ __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) pv_kick(node->cpu); } -/* - * Include the architecture specific callee-save thunk of the - * __pv_queued_spin_unlock(). This thunk is put together with - * __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock - * function close to each other sharing consecutive instruction cachelines. - * Alternatively, architecture specific version of __pv_queued_spin_unlock() - * can be defined. - */ -#include - #ifndef __pv_queued_spin_unlock __visible __lockfunc void __pv_queued_spin_unlock(struct qspinlock *lock) {