From patchwork Tue Jul 25 07:32:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 125421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp2325753vqg; Tue, 25 Jul 2023 01:40:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlFniZV379C7lTv3ZKbgznoQR16+nvzJAHwqiildThO64KSwo/OIEmmJ1LMGRiMdSbAHttIq X-Received: by 2002:a17:90b:4c42:b0:25c:18ad:6b82 with SMTP id np2-20020a17090b4c4200b0025c18ad6b82mr2304844pjb.21.1690274450301; Tue, 25 Jul 2023 01:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690274450; cv=none; d=google.com; s=arc-20160816; b=TrxLywhK6UQg6gtidlumElon5rxorC8M8S9IXtiSeUnfatfw039dd+REKkeXI73cXH 4HVFIB436wcpWcpxNv4qMBLsCALY2mgGtPLCyZMnVDz0Worf08SKTB9XP4vmFm/Vrfmv iZ6/2zA8IZz7mascJRArGzCvXn1ybDNLlOa3KLOJzDC7PKRdYNFhPp8RbTCWpPkcCelU RhMBcRMJ1rU6J6huZOOlxx42rDx2HLDo+SDfauluyeb/CSbM3936UQnwyLvXWxtOpNsy XUbs4ZcBuEQR2D4nJA5hgqqoFkxA0TYldTAkYIW2+9h5ISIS/53ltzh96osizqfm/CQc /2rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mZ6sQFR4gxSfqqcI9eTvgGGxfB1YmOHMmDnqYpBsC94=; fh=WlmesBPh9vy2WAKH+Oa8Mq1mzTGfSQhQroZj01YJT/8=; b=E4lSdXfKWP9Pv6g7RG02XJzkmI/8Iuj1Epbh2ocXAkfGq9nAOi1yoK8epUY7pZ4Ckf XNd1i4nMveP7FPgjHuin91Yvi9IeVawm+DF5jOmg+vq+v+vxYjyhlQRPz1FhkhIs1As8 urRXlywIKmgiPZc8AgZzfhPOzW3UFuJx5h3iG2vqV9MTWukb7dwbpZ5uOH50z4/jZkoW +u5JFbLrIpN7QSvcztG5fZHICRzOTUJD3krNTilkG45c75xGAZTD73V8JrXkaHcIGcfh 3B1PXhApaSGINxnoFk8uahzBBH2S1bQNKjOCSwWdmPYAZsdEpt+SzJoRVLsVk41lBvtj +TuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=GPDWnvxC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gm17-20020a17090b101100b0025c02c13dfbsi13367589pjb.100.2023.07.25.01.40.37; Tue, 25 Jul 2023 01:40:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=GPDWnvxC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232696AbjGYHfX (ORCPT + 99 others); Tue, 25 Jul 2023 03:35:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232335AbjGYHeK (ORCPT ); Tue, 25 Jul 2023 03:34:10 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 964701BD9 for ; Tue, 25 Jul 2023 00:32:49 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A388B6607106; Tue, 25 Jul 2023 08:32:47 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690270368; bh=RteFl78OPAscSrhmShuyzWWjAye9KXEUFGwSstlu+Ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GPDWnvxC40W5D6oHk33UAE+91Bmjr2HiowKQbzMrpQoJORcYkI0j/ahwIedlxd4xU FMkRVJWYwJiIzSo0IYNj3aorZJ0RjWwPbHknNmwy8aK4tVwNeysyxsKGluPm6OpnHR PsKgHA6rkQTUtIBygZqxTL/iHM4MjcdqH5NDexJESSDoilLNxTF7szoSZwU4RSEDQA 2q2kAwtqHSFlz3T/Gw08zzFdsgM3+IoEh4jpqwNFAQfjYGIkRZ0eXD/Dhlx+lNVHGy or6PPsd6c9QVjapmwlYdxilUH177tldd8vhd7CKPqShJmARq3oSXLaww4WpEpuM6wh ieG2+ReGv6ytw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, nfraprado@collabora.com, ehristev@collabora.com, CK Hu , Alexandre Mergnat Subject: [PATCH v7 02/11] drm/mediatek: dp: Move AUX and panel poweron/off sequence to function Date: Tue, 25 Jul 2023 09:32:25 +0200 Message-ID: <20230725073234.55892-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230725073234.55892-1-angelogioacchino.delregno@collabora.com> References: <20230725073234.55892-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772381221944966456 X-GMAIL-MSGID: 1772381221944966456 Everytime we run bridge detection and/or EDID read we run a poweron and poweroff sequence for both the AUX and the panel; moreover, this is also done when enabling the bridge in the .atomic_enable() callback. Move this power on/off sequence to a new mtk_dp_aux_panel_poweron() function as to commonize it. Note that, before this commit, in mtk_dp_bridge_atomic_enable() only the AUX was getting powered on but the panel was left powered off if the DP cable wasn't plugged in while now we unconditionally send a D0 request and this is done for two reasons: - First, whether this request fails or not, it takes the same time and anyway the DP hardware won't produce any error (or, if it does, it's ignorable because it won't block further commands) - Second, training the link between a sleeping/standby/unpowered display makes little sense. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Reviewed-by: CK Hu Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dp.c | 76 ++++++++++++------------------- 1 file changed, 30 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index c58b775877a3..77da0d002e9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1251,6 +1251,29 @@ static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute) val[2], AU_TS_CFG_DP_ENC0_P0_MASK); } +static void mtk_dp_aux_panel_poweron(struct mtk_dp *mtk_dp, bool pwron) +{ + if (pwron) { + /* power on aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL_LANE, + DP_PWR_STATE_MASK); + + /* power on panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); + usleep_range(2000, 5000); + } else { + /* power off panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); + usleep_range(2000, 3000); + + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + } +} + static void mtk_dp_power_enable(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE, @@ -1941,16 +1964,9 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) if (!mtk_dp->train_info.cable_plugged_in) return ret; - if (!enabled) { - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); + if (!enabled) + mtk_dp_aux_panel_poweron(mtk_dp, true); - /* power on panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); - } /* * Some dongles still source HPD when they do not connect to any * sink device. To avoid this, we need to read the sink count @@ -1962,16 +1978,8 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) if (DP_GET_SINK_COUNT(sink_count)) ret = connector_status_connected; - if (!enabled) { - /* power off panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - } + if (!enabled) + mtk_dp_aux_panel_poweron(mtk_dp, false); return ret; } @@ -1987,15 +1995,7 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, if (!enabled) { drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); - - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - - /* power on panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); + mtk_dp_aux_panel_poweron(mtk_dp, true); } new_edid = drm_get_edid(connector, &mtk_dp->aux.ddc); @@ -2015,15 +2015,7 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, } if (!enabled) { - /* power off panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - + mtk_dp_aux_panel_poweron(mtk_dp, false); drm_atomic_bridge_chain_post_disable(bridge, connector->state->state); } @@ -2183,15 +2175,7 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, return; } - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - - if (mtk_dp->train_info.cable_plugged_in) { - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); - } + mtk_dp_aux_panel_poweron(mtk_dp, true); /* Training */ ret = mtk_dp_training(mtk_dp);