[v5] arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain
Commit Message
CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN High and Low lines
from the SoC are routed through a mux on the SoM. The select lines need
to be set for the CAN signals to get connected to the transceivers on
the common processor board. Threfore, add respective mux, transceiver
dt nodes to add support for these CAN instances.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
Changelog v4->v5 : Modfied Mux Controller names
Link to v4 : https://lore.kernel.org/all/0070e00a-89c0-9b2b-8753-e1835b5aad15@ti.com/
.../dts/ti/k3-j721s2-common-proc-board.dts | 46 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 +++++
2 files changed, 58 insertions(+)
Comments
On 16:47-20230724, Bhavya Kapoor wrote:
> + main_mcan3_pins_default: main-mcan3-pins-default {
Could you make sure that the node names matches up with the json-schema
conversion:
https://lore.kernel.org/all/169021456020.3622493.10284534202541859578.robh@kernel.org/
@@ -29,6 +29,8 @@ aliases {
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
+ can3 = &main_mcan3;
+ can4 = &main_mcan5;
};
evm_12v0: fixedregulator-evm12v0 {
@@ -109,6 +111,22 @@ transceiver2: can-phy2 {
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux0 1>;
+ };
+
+ transceiver4: can-phy4 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux1 1>;
+ };
};
&main_pmx0 {
@@ -152,6 +170,20 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
+
+ main_mcan3_pins_default: main-mcan3-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
+ J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
+ >;
+ };
+
+ main_mcan5_pins_default: main-mcan5-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
+ J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
+ >;
+ };
};
&wkup_pmx2 {
@@ -460,3 +492,17 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&main_mcan3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan3_pins_default>;
+ phys = <&transceiver3>;
+};
+
+&main_mcan5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_pins_default>;
+ phys = <&transceiver4>;
+};
@@ -31,6 +31,18 @@ secure_ddr: optee@9e800000 {
};
};
+ mux0: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ mux1: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
+ };
+
transceiver0: can-phy0 {
/* standby pin has been grounded by default */
compatible = "ti,tcan1042";