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From: Komal Bajaj <quic_kbajaj@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
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CC: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Komal Bajaj <quic_kbajaj@quicinc.com>
Subject: [PATCH v5 1/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for
QDU1000/QRU1000
Date: Mon, 24 Jul 2023 14:11:50 +0530
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| Series |
soc: qcom: llcc: Add support for QDU1000/QRU1000
|
|
Commit Message
Komal Bajaj
July 24, 2023, 8:41 a.m. UTC
Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
nvmem-cells and nvmem-cell-names properties to support multiple
configurations for multi channel DDR.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
Comments
On 24/07/2023 10:41, Komal Bajaj wrote: > Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional > nvmem-cells and nvmem-cell-names properties to support multiple > configurations for multi channel DDR. > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 44892aa589fd..580f9a97ddf7 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -44,6 +45,14 @@ properties: interrupts: maxItems: 1 + nvmem-cells: + items: + - description: Reference to an nvmem node for multi channel DDR + + nvmem-cell-names: + items: + - const: multi-chan-ddr + required: - compatible - reg @@ -92,6 +101,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: