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Sat, 22 Jul 2023 06:20:44 -0500 From: Nikunj A Dadhania To: , CC: , , , , , , Subject: [PATCH v3 10/14] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests Date: Sat, 22 Jul 2023 16:49:05 +0530 Message-ID: <20230722111909.15166-11-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230722111909.15166-1-nikunj@amd.com> References: <20230722111909.15166-1-nikunj@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT075:EE_|CH2PR12MB4857:EE_ X-MS-Office365-Filtering-Correlation-Id: f6c0188d-c07d-4b61-7f37-08db8aa5b315 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2aES4z/uDbCjQF3M51FGr2Pnk6su+HFlfPFwzdtwvNkAwhPkD77mrJ/+0nMD1FBR+BI67zCAu6Vg6sF3CyUhccv0us7uM9zaSKk4k4jgnXNasEjksW22egJd1aDKNV25sZL8u+Vnd1XOH0Skx0onpwg0ibvpcgj4gQHj4h/MGxJ5wLkE8nW7vx3Tl6VquhEUoTmEXCidfJ9LuHs7ZHMT2MnFjBLTSHBmtXFs7JLlca2VWMd6DipuS9V8t022JU1RFGuN8GMkyMPXhHRrZmFuHm//cSNcZJ8WidbGhj1EGKhXa6ck6gRGd0ROzvVY2aAcqAzjs6BuTfMWaBeiIeCqVwTue4AmnZ6Gd2EZ0+t8pnGmLhK5aEjC6y3pcPTpF22xCkAa5kzoSx/tX05laU4mTwEpXWAjP/jzihpcqDymYhFb51sej8BaCIOgFGa6HADGDs9tzu0kjhWPHa7vTVlRB12J9HyH/Xi0T6BmXYViuR0fn7dW7Fzfrh3cwJ0cbE7zL1jmv0jOIqWqTRtgLxnh3Ixm0SZotUgecy/Cw0M6JDnKQQ+KQswkq3WVkvk7//H4WMKO6Hiwvgt8KwScO9BnlrV4pSaO7NZbwG6SHYb86ktUG+8V7GLjq/KongplNNNeLhrkhFSHDrFROCy7ha6rOeP3ycEYMuJckuzu+EaWjE6AjcXdoW1+nTjuzkFr6cFrlcjE6YHR8BNw2sHS5KI2mz9QJv32gdfde02cS4vgY3GutUXVZ7ejzpuHfVq5Oo7TBJ/ETx7exWb9Z0QlufVhMw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199021)(82310400008)(40470700004)(46966006)(36840700001)(40460700003)(81166007)(40480700001)(356005)(36860700001)(36756003)(426003)(2616005)(47076005)(83380400001)(16526019)(8936002)(8676002)(5660300002)(110136005)(478600001)(54906003)(4326008)(316002)(70586007)(70206006)(41300700001)(26005)(186003)(336012)(1076003)(6666004)(7696005)(2906002)(82740400003)(36900700001);DIR:OUT;SFP:1101; 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MSR_IA32_TSC related accesses should not exit to the hypervisor for such guests. Accesses to MSR_IA32_TSC needs special handling in the #VC handler for the guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored, and reads of MSR_IA32_TSC should return the result of the RDTSC instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky --- arch/x86/kernel/sev.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index d55562cd395d..2d42822fa01c 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1729,6 +1729,30 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) /* Is it a WRMSR? */ exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; + /* + * TSC related accesses should not exit to the hypervisor when a + * guest is executing with SecureTSC enabled, so special handling + * is required for accesses of MSR_IA32_TSC: + * + * Writes: Writing to MSR_IA32_TSC can cause subsequent reads + * of the TSC to return undefined values, so ignore all + * writes. + * Reads: Reads of MSR_IA32_TSC should return the current TSC + * value, use the value returned by RDTSC. + */ + if (regs->cx == MSR_IA32_TSC && cc_platform_has(CC_ATTR_GUEST_SECURE_TSC)) { + u64 tsc; + + if (exit_info_1) + return ES_OK; + + tsc = rdtsc(); + regs->ax = UINT_MAX & tsc; + regs->dx = UINT_MAX & (tsc >> 32); + + return ES_OK; + } + ghcb_set_rcx(ghcb, regs->cx); if (exit_info_1) { ghcb_set_rax(ghcb, regs->ax);