Message ID | 20230720202813.3269888-1-john.allen@amd.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp3377479vqt; Thu, 20 Jul 2023 14:02:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlFpTD931bfiQfTiWrB+3SmhLjryVZo+LouQWdvPQn0ydl4jUpbtx5LOIUF/cGbhz5YwyBp6 X-Received: by 2002:a17:902:7448:b0:1b9:ea60:cd89 with SMTP id e8-20020a170902744800b001b9ea60cd89mr107160plt.7.1689886929563; Thu, 20 Jul 2023 14:02:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689886929; cv=pass; d=google.com; s=arc-20160816; b=shz6KzhUJ2PotLl9moBTgyvoQfGUAGFVeizPPrnjDX//hVrxmiUQTE0ipzKgkaWw52 g7vT3je154/PeYAac/WH5cXThVsYyX8Sj6szxMaoGY1SVePpkwmJ3bECjopxzChk5Lyi zyovOOWuiuxIRzYNCp9pbgci7Auq6L9QhDQ8XSNoiz67DDhT4FMSPN0SyZIjW6GoEUe9 1ZVITG2YhuQCQM6P726RC0rvdzYpthdERrJZNvJnmQR1fjRP9nP6Ye4PM9YP7AiA0h89 HKp5J4QI7OvNEIZ+R8ti76Ou9T4flItzGOnQI+HyNdDZUHXl2aI5aXA2K39f3hfzr7+u GuMg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=OoM/PHiNwVCxv2JrvAPeXjDXTa6wF1QZnD03AwUPfRk=; fh=TUonFMuZnVmIRf7WEueyBpCN5f4MjBO5JAd4LQKytq4=; b=FEQPBE/IkfPg/wZMpIqioKtxxfY7ECI4iDsAUjYgx9MEoXWN0n3NAeINwW3xG3Lxrs 5hxgENHpGJiLF2mPRgA87weglwQrtKITtogVT0/Ufywfoyl+yO/AoEWXb67ol+LG0FaF U3F9OO6jSLJRqdkEDtfDCse5dvQTS4qXL4AJYY05xkiLP1moMUPEq43Tqelx3WKVTY7D xvb0ZY5+90/++Ey7NOd3nrvYsvq2rslw6fI2lfr3MFK8FXVWIx6PphnNL2kKB4lLWDk5 Z4jszoDOMl+jrysPbAPQooQcpnTpfwG6VtUCU+XW2+b4TqklIpKn09/ze995Im3qdjYz 8UUg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Q5LLVxGu; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q8-20020a170902dac800b001b530ede2besi1628918plx.614.2023.07.20.14.01.55; Thu, 20 Jul 2023 14:02:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Q5LLVxGu; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230217AbjGTU2f (ORCPT <rfc822;assdfgzxcv4@gmail.com> + 99 others); Thu, 20 Jul 2023 16:28:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229517AbjGTU2c (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 20 Jul 2023 16:28:32 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6F78272A; Thu, 20 Jul 2023 13:28:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SFeoc/GMaT4npENXHiKaPebbYtMwJcwdzc+zILgF8HXRe3AKou/+ECn6D/hCtuqhVkOAnWX7SRnlmFr7zZ8MnvizuF5CyKS/q6FCq3R4+gKCpG1mAnMdih2frP94Nj8P8BDmu3rC6YC5NUvtX95KcAqqzAli2h3xblQUx+KraK3veXY+ONlX7VgcKsK2IQoIUe6NsKsP0Yhcu7Tx4AmLeKWdBJSf5STTCqsYpzS5WA1yyJku4j6lsFb0QYyfFOVNdrwePdO82tjHd8/6oKEybsDQJrLSOVb/Yx9YuHkN+cKoJUI8p0RnO9yYP5UcVandq7RTBpvkKiFHv9vgw446Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OoM/PHiNwVCxv2JrvAPeXjDXTa6wF1QZnD03AwUPfRk=; b=HfS905KRbJTtOC4vSt1Eue1ltMUS6fHtywYAieQgQqW0S9HIj4kGf7Xn9K3DL+n5F6hyOSpWRJwoxLHgwe1R+X+quxLj/o5cRUGRa8/BbgcYCZG1ugXbHfuCZFPrFSRMn2BEVfNPCheh/zGlsTQSgy9PvJNsuVRDgQ8+dzspf1UDFzgqUo+J1C58/XgI7vzf+Q8NT7PLm/xd3Gq7ILLRxrcNNAp3TA/CXNL/oXatTvj5l1lqkNRcdiYsezFyUl/k/l/lXZVvGVolDlHsThp2vsmj5gvwqpOlz5awvtyc5ZATFsjh8Rwm73BvEb7EPrC+75HemQ4P3E0gh0pXRedCRg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=alien8.de smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OoM/PHiNwVCxv2JrvAPeXjDXTa6wF1QZnD03AwUPfRk=; b=Q5LLVxGuPLe9eCMB5jDiRvYhEh1dvjm84gPyes/O0mGmM78o1FBLYN9lz2XX55H/bIKyHpw8nBX9ThdSoh4os92aSfvHxZBbq7Npp9sMcz5eBoHCK8QIkAgZnv579u/26oa1cG02AUgCtNHgtEW5sj3/jkSUraAIYp9rukWgCVs= Received: from BN9PR03CA0356.namprd03.prod.outlook.com (2603:10b6:408:f6::31) by DM4PR12MB7718.namprd12.prod.outlook.com (2603:10b6:8:102::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.24; Thu, 20 Jul 2023 20:28:27 +0000 Received: from BN8NAM11FT093.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f6:cafe::ce) by BN9PR03CA0356.outlook.office365.com (2603:10b6:408:f6::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.25 via Frontend Transport; Thu, 20 Jul 2023 20:28:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT093.mail.protection.outlook.com (10.13.177.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6609.28 via Frontend Transport; Thu, 20 Jul 2023 20:28:26 +0000 Received: from jallen-jump-host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 20 Jul 2023 15:28:25 -0500 From: John Allen <john.allen@amd.com> To: <bp@alien8.de>, <linux-kernel@vger.kernel.org> CC: <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>, <x86@kernel.org>, John Allen <john.allen@amd.com>, <stable@vger.kernel.org> Subject: [PATCH] x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE Date: Thu, 20 Jul 2023 20:28:13 +0000 Message-ID: <20230720202813.3269888-1-john.allen@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT093:EE_|DM4PR12MB7718:EE_ X-MS-Office365-Filtering-Correlation-Id: 17a1e73b-56f1-44b9-bbb8-08db895fdf4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u0rTj2uiBmC7j08AnhbRxtsAHSpM2OhlarWRWnCxMKR4YspAVHtHBhbS6gM/BV3ssFebvTaDiPk1znx+mDx70KjHTR4RST2XBDVDamd39nXwSiGmcHrKDHagcaKrSlWM6lHPefmufJIxub7bc/DZccdZJ/6uhyqA2KHksR4fKR0sQAKkFHg6UprdIYF9g7ZcD+JDnI9UL8y8+GrW+YletvMKUmoc86Rx58Mqys8NK6Q5Lut1TGvW6HXJEWMBjImUMdC2qp+grQ2J663ZlpN3qHzN8Jc665aYYkQcMHz6/1iUp37XgLSswjWzw4y8BUOaU+orYDBPDhnLNSQa6dn3j2fW/H93ohGWLx8iZziKYyeyg5/WMfsFKzLmbyd2g1Gwx6XngCpb6qSMYSETVAQrr5vwr/fA6Jw5UIfV7QxVYiuPR1Z4vEQ+eTZ47i4Z0ceYnmfDo9Roc+avhO73PkQLA5uUUCAGnpajoczXfasU/7gD/Su20P34ufjt2j799sLKuYLtDlJmjmewjrLbaZ8HFhgQ0TwUSlqiP8yIXFVYxpirZov+ZJSBPIu9mws+Y/eDGRBFVz6hxIaGLmFYmKHeNsmMZ5zYJLcHuxoRdMPjtda0j8dI4sxTwgmONmDULjQHJHm26iowFJQ757zIOJiwBn+bdP9JRpIL+nDvy2HjVd7FricA+6oCtncjfzNdtGjJjtCghgoBZdrgrHnd9u0XKMwRNUGxgW94/Ciw8SSWLdZhTyvjRmDCmz0bY3W30J0SS+v5BEEFENgkZ1dhcNL/9g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(376002)(39860400002)(346002)(136003)(82310400008)(451199021)(36840700001)(46966006)(40470700004)(81166007)(82740400003)(356005)(40480700001)(40460700003)(7696005)(6666004)(86362001)(336012)(1076003)(8676002)(186003)(26005)(16526019)(44832011)(316002)(41300700001)(5660300002)(70586007)(70206006)(4326008)(54906003)(4744005)(2906002)(110136005)(8936002)(83380400001)(36860700001)(2616005)(36756003)(426003)(478600001)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2023 20:28:26.3834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17a1e73b-56f1-44b9-bbb8-08db895fdf4c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT093.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7718 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771974877123476180 X-GMAIL-MSGID: 1771974877123476180 |
Series |
x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE
|
|
Commit Message
John Allen
July 20, 2023, 8:28 p.m. UTC
Future AMD cpus will have microcode patches that exceed the current
limit of three 4K pages. Increase substantially to avoid future size
increases.
Signed-off-by: John Allen <john.allen@amd.com>
Cc: stable@vger.kernel.org
---
arch/x86/include/asm/microcode_amd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 20. 07. 23, 22:28, John Allen wrote: > Future AMD cpus will have microcode patches that exceed the current > limit of three 4K pages. Increase substantially to avoid future size > increases. Hi, so with my current distro (openSUSE TW): $ zgrep NODES_SHIFT /proc/config.gz CONFIG_NODES_SHIFT=10 This: static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE]; is now 32M instead of 12M. That is a complete waste on my _one_ node system. Can we make amd_ucode_patch dynamic first, depending on num_online_nodes()? > Signed-off-by: John Allen <john.allen@amd.com> > Cc: stable@vger.kernel.org > --- > arch/x86/include/asm/microcode_amd.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h > index e6662adf3af4..e3d5f5ae2f46 100644 > --- a/arch/x86/include/asm/microcode_amd.h > +++ b/arch/x86/include/asm/microcode_amd.h > @@ -41,7 +41,7 @@ struct microcode_amd { > unsigned int mpb[]; > }; > > -#define PATCH_MAX_SIZE (3 * PAGE_SIZE) > +#define PATCH_MAX_SIZE (8 * PAGE_SIZE) > > #ifdef CONFIG_MICROCODE_AMD > extern void __init load_ucode_amd_bsp(unsigned int family); thanks,
On Fri, Jul 21, 2023 at 06:47:39AM +0200, Jiri Slaby wrote: > is now 32M instead of 12M. That is a complete waste on my _one_ node system. > Can we make amd_ucode_patch dynamic first, depending on num_online_nodes()? I have a small set which gets rid of all those arrays - I just need to finish it. :-(
Remove stable@. This below seems to work here on a couple of machines. Can you run it too pls to confirm? Thx. --- From: "Borislav Petkov (AMD)" <bp@alien8.de> Date: Wed, 7 Jun 2023 21:01:06 +0200 Subject: [PATCH] x86/microcode/AMD: Rip out static buffers Load straight from the containers (initrd or builtin, for example). There's no need to cache the patch per node. This even simplifies the code a bit with the opportunity for more cleanups later. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> --- arch/x86/include/asm/microcode_amd.h | 6 +- arch/x86/kernel/cpu/microcode/amd.c | 91 +++++++++------------------- arch/x86/kernel/cpu/microcode/core.c | 4 +- 3 files changed, 31 insertions(+), 70 deletions(-) diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index e6662adf3af4..a995b7685223 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -44,13 +44,11 @@ struct microcode_amd { #define PATCH_MAX_SIZE (3 * PAGE_SIZE) #ifdef CONFIG_MICROCODE_AMD -extern void __init load_ucode_amd_bsp(unsigned int family); -extern void load_ucode_amd_ap(unsigned int family); +extern void load_ucode_amd_early(unsigned int cpuid_1_eax); extern int __init save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); #else -static inline void __init load_ucode_amd_bsp(unsigned int family) {} -static inline void load_ucode_amd_ap(unsigned int family) {} +static inline void load_ucode_amd_early(unsigned int cpuid_1_eax) {} static inline int __init save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } static inline void reload_ucode_amd(unsigned int cpu) {} diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 87208e46f7ed..a28b103256ff 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -56,9 +56,6 @@ struct cont_desc { static u32 ucode_new_rev; -/* One blob per node. */ -static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE]; - /* * Microcode patch container file is prepended to the initrd in cpio * format. See Documentation/arch/x86/microcode.rst @@ -415,20 +412,17 @@ static int __apply_microcode_amd(struct microcode_amd *mc) * * Returns true if container found (sets @desc), false otherwise. */ -static bool early_apply_microcode(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch) +static bool early_apply_microcode(u32 cpuid_1_eax, void *ucode, size_t size) { struct cont_desc desc = { 0 }; - u8 (*patch)[PATCH_MAX_SIZE]; struct microcode_amd *mc; u32 rev, dummy, *new_rev; bool ret = false; #ifdef CONFIG_X86_32 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); - patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); #else new_rev = &ucode_new_rev; - patch = &amd_ucode_patch[0]; #endif desc.cpuid_1_eax = cpuid_1_eax; @@ -452,9 +446,6 @@ static bool early_apply_microcode(u32 cpuid_1_eax, void *ucode, size_t size, boo if (!__apply_microcode_amd(mc)) { *new_rev = mc->hdr.patch_id; ret = true; - - if (save_patch) - memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE)); } return ret; @@ -507,7 +498,7 @@ static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret = cp; } -void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax) +static void apply_ucode_from_containers(unsigned int cpuid_1_eax) { struct cpio_data cp = { }; @@ -515,42 +506,12 @@ void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax) if (!(cp.data && cp.size)) return; - early_apply_microcode(cpuid_1_eax, cp.data, cp.size, true); + early_apply_microcode(cpuid_1_eax, cp.data, cp.size); } -void load_ucode_amd_ap(unsigned int cpuid_1_eax) +void load_ucode_amd_early(unsigned int cpuid_1_eax) { - struct microcode_amd *mc; - struct cpio_data cp; - u32 *new_rev, rev, dummy; - - if (IS_ENABLED(CONFIG_X86_32)) { - mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch); - new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); - } else { - mc = (struct microcode_amd *)amd_ucode_patch; - new_rev = &ucode_new_rev; - } - - native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); - - /* - * Check whether a new patch has been saved already. Also, allow application of - * the same revision in order to pick up SMT-thread-specific configuration even - * if the sibling SMT thread already has an up-to-date revision. - */ - if (*new_rev && rev <= mc->hdr.patch_id) { - if (!__apply_microcode_amd(mc)) { - *new_rev = mc->hdr.patch_id; - return; - } - } - - find_blobs_in_containers(cpuid_1_eax, &cp); - if (!(cp.data && cp.size)) - return; - - early_apply_microcode(cpuid_1_eax, cp.data, cp.size, false); + return apply_ucode_from_containers(cpuid_1_eax); } static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size); @@ -578,23 +539,6 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) return 0; } -void reload_ucode_amd(unsigned int cpu) -{ - u32 rev, dummy __always_unused; - struct microcode_amd *mc; - - mc = (struct microcode_amd *)amd_ucode_patch[cpu_to_node(cpu)]; - - rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); - - if (rev < mc->hdr.patch_id) { - if (!__apply_microcode_amd(mc)) { - ucode_new_rev = mc->hdr.patch_id; - pr_info("reload patch_level=0x%08x\n", ucode_new_rev); - } - } -} - /* * a small, trivial cache of per-family ucode patches */ @@ -655,6 +599,28 @@ static struct ucode_patch *find_patch(unsigned int cpu) return cache_find_patch(equiv_id); } +void reload_ucode_amd(unsigned int cpu) +{ + u32 rev, dummy __always_unused; + struct microcode_amd *mc; + struct ucode_patch *p; + + p = find_patch(cpu); + if (!p) + return; + + mc = p->data; + + rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); + + if (rev < mc->hdr.patch_id) { + if (!__apply_microcode_amd(mc)) { + ucode_new_rev = mc->hdr.patch_id; + pr_info("reload patch_level=0x%08x\n", ucode_new_rev); + } + } +} + static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { struct cpuinfo_x86 *c = &cpu_data(cpu); @@ -875,9 +841,6 @@ static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t siz continue; ret = UCODE_NEW; - - memset(&amd_ucode_patch[nid], 0, PATCH_MAX_SIZE); - memcpy(&amd_ucode_patch[nid], p->data, min_t(u32, p->size, PATCH_MAX_SIZE)); } return ret; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 3afcf3de0dd4..192adf5f948e 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -172,7 +172,7 @@ void __init load_ucode_bsp(void) if (intel) load_ucode_intel_bsp(); else - load_ucode_amd_bsp(cpuid_1_eax); + load_ucode_amd_early(cpuid_1_eax); } static bool check_loader_disabled_ap(void) @@ -200,7 +200,7 @@ void load_ucode_ap(void) break; case X86_VENDOR_AMD: if (x86_family(cpuid_1_eax) >= 0x10) - load_ucode_amd_ap(cpuid_1_eax); + load_ucode_amd_early(cpuid_1_eax); break; default: break;
On Fri, Jul 21, 2023 at 05:49:42PM +0200, Borislav Petkov wrote: > Remove stable@. > > This below seems to work here on a couple of machines. > > Can you run it too pls to confirm? > > Thx. Yes, this appears to be working on my machine as well. Tested-by: John Allen <john.allen@amd.com>
On Fri, Jul 21, 2023 at 11:42:03AM -0500, John Allen wrote: > Yes, this appears to be working on my machine as well. > > Tested-by: John Allen <john.allen@amd.com> Thanks, I'll queue it.
diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index e6662adf3af4..e3d5f5ae2f46 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -41,7 +41,7 @@ struct microcode_amd { unsigned int mpb[]; }; -#define PATCH_MAX_SIZE (3 * PAGE_SIZE) +#define PATCH_MAX_SIZE (8 * PAGE_SIZE) #ifdef CONFIG_MICROCODE_AMD extern void __init load_ucode_amd_bsp(unsigned int family);