Message ID | 20230719-mcrc-upstream-v2-3-4152b987e4c2@ti.com |
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State | New |
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Miller" <davem@davemloft.net>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Tero Kristo <kristo@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@foss.st.com> CC: <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-stm32@st-md-mailman.stormreply.com>, Kamlesh Gurudasani <kamlesh@ti.com> X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1691695767; l=2556; i=kamlesh@ti.com; s=20230614; h=from:subject:message-id; bh=/LLW6Kt8hKHcCDBDMh4ZLatVHlvY99JTcrS11iXF92Q=; b=QAiGHrrUXCFcvkOJiB1SjSy/6++4XYHeiT8zb0bOyW48+JCWXp80jbX3m93QwhnqWPI9h7hI7 IXdAfwnI9YdBIHWUapCYudmteTuxXBb8HzKSCJxrdlKb8rTf3TjB1Aq X-Developer-Key: i=kamlesh@ti.com; a=ed25519; pk=db9XKPVWDGJVqj2jDqgnPQd6uQf3GZ3oaQa4bq1odGo= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773876662741484109 X-GMAIL-MSGID: 1773876662741484109 |
Series |
Add support for Texas Instruments MCRC64 engine
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Commit Message
Kamlesh Gurudasani
Aug. 10, 2023, 7:28 p.m. UTC
Add binding for Texas Instruments MCRC64
MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
according to the ISO 3309 standard.
The ISO 3309 64-bit CRC model parameters are as follows:
Generator Polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial Value: 0x000000000000001B
Initial value: 0x0000000000000000
Reflected Input: False
Reflected Output: False
Xor Final: 0x0000000000000000
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 47 +++++++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 5 +++++
2 files changed, 52 insertions(+)
Comments
On Fri, Aug 11, 2023 at 12:58:50AM +0530, Kamlesh Gurudasani wrote: > Add binding for Texas Instruments MCRC64 > > MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC) > according to the ISO 3309 standard. > > The ISO 3309 64-bit CRC model parameters are as follows: > Generator Polynomial: x^64 + x^4 + x^3 + x + 1 > Polynomial Value: 0x000000000000001B > Initial value: 0x0000000000000000 > Reflected Input: False > Reflected Output: False > Xor Final: 0x0000000000000000 > > Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com> > --- > Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 47 +++++++++++++++++++++++++++++++++++++++++++++++ > MAINTAINERS | 5 +++++ > 2 files changed, 52 insertions(+) > > diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > new file mode 100644 > index 000000000000..38bc7efebd68 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments MCRC64 > + > +description: The MCRC64 engine calculates 64-bit cyclic redundancy checks A newline after "description" please. > + (CRC) according to the ISO 3309 standard. > + > +maintainers: > + - Kamlesh Gurudasani <kamlesh@ti.com> > + > +properties: > + compatible: > + const: ti,am62-mcrc64 Is the am62 an SoC or a family of SoCs? I googled a wee bit for am62 & there seems to be an am625 and an am623? Otherwise, this looks good to me. > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/ti,sci_pm_domain.h> > + > + crc@30300000 { > + compatible = "ti,am62-mcrc64"; > + reg = <0x30300000 0x1000>; > + clocks = <&k3_clks 116 0>; > + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; > + }; > + > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 02a3192195af..66b51f43d196 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -21481,6 +21481,11 @@ S: Maintained > F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml > F: drivers/iio/adc/ti-lmp92064.c > > +TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER > +M: Kamlesh Gurudasani <kamlesh@ti.com> > +S: Maintained > +F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > + > TI PCM3060 ASoC CODEC DRIVER > M: Kirill Marinushkin <kmarinushkin@birdec.com> > L: alsa-devel@alsa-project.org (moderated for non-subscribers) > > -- > 2.34.1 >
On Fri, Aug 11, 2023 at 04:34:33PM +0100, Conor Dooley wrote: > On Fri, Aug 11, 2023 at 12:58:50AM +0530, Kamlesh Gurudasani wrote: > > Add binding for Texas Instruments MCRC64 > > > > MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC) > > according to the ISO 3309 standard. > > > > The ISO 3309 64-bit CRC model parameters are as follows: > > Generator Polynomial: x^64 + x^4 + x^3 + x + 1 > > Polynomial Value: 0x000000000000001B > > Initial value: 0x0000000000000000 > > Reflected Input: False > > Reflected Output: False > > Xor Final: 0x0000000000000000 > > > > Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com> > > --- > > Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 47 +++++++++++++++++++++++++++++++++++++++++++++++ > > MAINTAINERS | 5 +++++ > > 2 files changed, 52 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > > new file mode 100644 > > index 000000000000..38bc7efebd68 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > > @@ -0,0 +1,47 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Texas Instruments MCRC64 > > + > > +description: The MCRC64 engine calculates 64-bit cyclic redundancy checks > > A newline after "description" please. > > > + (CRC) according to the ISO 3309 standard. > > + > > +maintainers: > > + - Kamlesh Gurudasani <kamlesh@ti.com> > > + > > +properties: > > + compatible: > > + const: ti,am62-mcrc64 > > Is the am62 an SoC or a family of SoCs? I googled a wee bit for am62 & > there seems to be an am625 and an am623? Or is it an am62p5, in which case the compatible should contain ti,am62p5 I suppose. Sorry for my confusion here, its not really clear me too since I've been seeing many different-but-similar product names the last few days. Thanks, Conor. > > Otherwise, this looks good to me. > > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - power-domains > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/soc/ti,sci_pm_domain.h> > > + > > + crc@30300000 { > > + compatible = "ti,am62-mcrc64"; > > + reg = <0x30300000 0x1000>; > > + clocks = <&k3_clks 116 0>; > > + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; > > + }; > > + > > +... > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 02a3192195af..66b51f43d196 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -21481,6 +21481,11 @@ S: Maintained > > F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml > > F: drivers/iio/adc/ti-lmp92064.c > > > > +TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER > > +M: Kamlesh Gurudasani <kamlesh@ti.com> > > +S: Maintained > > +F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > > + > > TI PCM3060 ASoC CODEC DRIVER > > M: Kirill Marinushkin <kmarinushkin@birdec.com> > > L: alsa-devel@alsa-project.org (moderated for non-subscribers) > > > > -- > > 2.34.1 > >
diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml new file mode 100644 index 000000000000..38bc7efebd68 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments MCRC64 + +description: The MCRC64 engine calculates 64-bit cyclic redundancy checks + (CRC) according to the ISO 3309 standard. + +maintainers: + - Kamlesh Gurudasani <kamlesh@ti.com> + +properties: + compatible: + const: ti,am62-mcrc64 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + crc@30300000 { + compatible = "ti,am62-mcrc64"; + reg = <0x30300000 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 02a3192195af..66b51f43d196 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21481,6 +21481,11 @@ S: Maintained F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml F: drivers/iio/adc/ti-lmp92064.c +TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER +M: Kamlesh Gurudasani <kamlesh@ti.com> +S: Maintained +F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml + TI PCM3060 ASoC CODEC DRIVER M: Kirill Marinushkin <kmarinushkin@birdec.com> L: alsa-devel@alsa-project.org (moderated for non-subscribers)