mbox series

[GIT,PULL] irqchip fixes for 6.5, take ]1

Message ID 20230717113857.304919-1-maz@kernel.org
State New
Headers
Series [GIT,PULL] irqchip fixes for 6.5, take ]1 |

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-6.5-1

Message

Marc Zyngier July 17, 2023, 11:38 a.m. UTC 
  Thomas,

Here's a small set of irqchip fixes for 6.5. Two workarounds for
broken HW, and pair of bug fixes.

Please pull,

	M.

The following changes since commit a82f3119d543406ed5b242deabf83cdecb9fe523:

  Merge branch irq/misc-6.5 into irq/irqchip-next (2023-06-21 13:53:41 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-6.5-1

for you to fetch changes up to 6fe5c68ee6a1aae0ef291a56001e7888de547fa2:

  irqchip/gic-v3: Workaround for GIC-700 erratum 2941627 (2023-07-11 09:04:31 +0100)

----------------------------------------------------------------
irqchip fixes for 6.5, take #1

- Work around an erratum on GIC700, where a race between a CPU
  handling a wake-up interrupt, a change of affinity, and another
  CPU going to sleep can result in a lack of wake-up event on the
  next interrupt.

- Fix the locking required on a VPE for GICv4

- Enable Rockchip 3588001 erratum workaround for RK3588S

- Fix the irq-bcm6345-l1 assumtions of the boot CPU always be
  the first CPU in the system

----------------------------------------------------------------
Jonas Gorski (1):
      irq-bcm6345-l1: Do not assume a fixed block to cpu mapping

Lorenzo Pieralisi (1):
      irqchip/gic-v3: Workaround for GIC-700 erratum 2941627

Marc Zyngier (1):
      irqchip/gic-v4.1: Properly lock VPEs when doing a directLPI invalidation

Sebastian Reichel (1):
      irqchip/gic-v3: Enable Rockchip 3588001 erratum workaround for RK3588S

 Documentation/arm64/silicon-errata.rst |  3 ++
 drivers/irqchip/irq-bcm6345-l1.c       | 14 +++---
 drivers/irqchip/irq-gic-v3-its.c       | 78 +++++++++++++++++++++-------------
 drivers/irqchip/irq-gic-v3.c           | 62 ++++++++++++++++++++++++++-
 4 files changed, 117 insertions(+), 40 deletions(-)

Comments

tip-bot2 for Thomas Gleixner July 24, 2023, 8:35 a.m. UTC | #1 
The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     de990908521073d98a46ad0e29885df447e95242
Gitweb:        https://git.kernel.org/tip/de990908521073d98a46ad0e29885df447e95242
Author:        Thomas Gleixner <tglx@linutronix.de>
AuthorDate:    Mon, 24 Jul 2023 10:27:43 +02:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 24 Jul 2023 10:27:43 +02:00

Merge tag 'irqchip-fixes-6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

  - Work around an erratum on GIC700, where a race between a CPU
    handling a wake-up interrupt, a change of affinity, and another
    CPU going to sleep can result in a lack of wake-up event on the
    next interrupt.

  - Fix the locking required on a VPE for GICv4

  - Enable Rockchip 3588001 erratum workaround for RK3588S

  - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be
    the first CPU in the system

Link: https://lore.kernel.org/lkml/20230717113857.304919-1-maz@kernel.org
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