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[v3,15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC

Message ID	20230717-topic-branch_aon_cleanup-v3-15-3e31bce9c626@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Wed, 20 Dec 2023 01:30:56 +0100 Subject: [PATCH v3 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230717-topic-branch_aon_cleanup-v3-15-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> Cc: Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>
Series	Unregister critical branch clocks + some RPM \| [v3,00/15] Unregister critical branch clocks + some RPM [v3,01/15] clk: qcom: branch: Add a helper for setting the enable bit [v3,02/15] clk: qcom: Use qcom_branch_set_clk_en() [v3,03/15] clk: qcom: gcc-sm6375: Unregister critical clocks [v3,04/15] clk: qcom: gcc-sm6375: Add runtime PM [v3,05/15] clk: qcom: gpucc-sm6375: Unregister critical clocks [v3,06/15] clk: qcom: gpucc-sm6115: Unregister critical clocks [v3,07/15] clk: qcom: gpucc-sm6115: Add runtime PM [v3,08/15] clk: qcom: gcc-sm6115: Unregister critical clocks [v3,09/15] clk: qcom: gcc-sm6115: Add runtime PM [v3,10/15] clk: qcom: gcc-qcm2290: Unregister critical clocks [v3,11/15] clk: qcom: gcc-qcm2290: Add runtime PM [v3,12/15] arm64: dts: qcom: sm6375: Add VDD_CX to GCC [v3,13/15] arm64: dts: qcom: qcm2290: Add VDD_CX to GCC [v3,14/15] arm64: dts: qcom: sm6115: Add VDD_CX to GCC [v3,15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC

Commit Message

Konrad Dybcio Dec. 20, 2023, 12:30 a.m. UTC

  The GPU_CC block is powered by VDD_CX. Link the power domain and
provide a reasonable minimum vote (lowest available on the platform)
to ensure the registers within are accessible.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 30b140e1cec0..ec9a74acc69c 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -1723,6 +1723,8 @@  gpucc: clock-controller@5990000 {
 			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			power-domains = <&rpmpd SM6115_VDDCX>;
+			required-opps = <&rpmpd_opp_low_svs>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;