Message ID | 20230715010407.1751715-4-fabrizio.castro.jz@renesas.com |
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State | New |
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spi: rzv2m-csi: Code refactoring
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Commit Message
Fabrizio Castro
July 15, 2023, 1:04 a.m. UTC
Clock "csiclk" gets divided by 2 * CSI_CLKSEL_CKS in order to generate
the serial clock (output from master), with CSI_CLKSEL_CKS ranging from
0x1 (that means "csiclk" is divided by 2) to 0x3FFF ("csiclk" is divided
by 32766). CSI_CKS_MAX is used for referring to the setting
corresponding to the maximum frequency divider.
Value 0x3FFF for CSI_CKS_MAX doesn't really means much to the reader
without an explanation and a more readable definition.
Add a comment with a meaningful description and also replace value
0x3FFF with the corresponding GENMASK, to make it very clear what the
macro means.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
drivers/spi/spi-rzv2m-csi.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
Comments
On Sat, Jul 15, 2023 at 3:04 AM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > Clock "csiclk" gets divided by 2 * CSI_CLKSEL_CKS in order to generate > the serial clock (output from master), with CSI_CLKSEL_CKS ranging from > 0x1 (that means "csiclk" is divided by 2) to 0x3FFF ("csiclk" is divided > by 32766). CSI_CKS_MAX is used for referring to the setting > corresponding to the maximum frequency divider. > Value 0x3FFF for CSI_CKS_MAX doesn't really means much to the reader > without an explanation and a more readable definition. > > Add a comment with a meaningful description and also replace value > 0x3FFF with the corresponding GENMASK, to make it very clear what the > macro means. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/spi/spi-rzv2m-csi.c b/drivers/spi/spi-rzv2m-csi.c index 3931045a85eb..621774949bde 100644 --- a/drivers/spi/spi-rzv2m-csi.c +++ b/drivers/spi/spi-rzv2m-csi.c @@ -65,7 +65,12 @@ #define CSI_FIFO_SIZE_BYTES 32 #define CSI_FIFO_HALF_SIZE 16 #define CSI_EN_DIS_TIMEOUT_US 100 -#define CSI_CKS_MAX 0x3FFF +/* + * Clock "csiclk" gets divided by 2 * CSI_CLKSEL_CKS in order to generate the + * serial clock (output from master), with CSI_CLKSEL_CKS ranging from 0x1 (that + * means "csiclk" is divided by 2) to 0x3FFF ("csiclk" is divided by 32766). + */ +#define CSI_CKS_MAX GENMASK(13, 0) #define UNDERRUN_ERROR BIT(0) #define OVERFLOW_ERROR BIT(1)