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[v5,9/9] MAINTAINERS: Add entry for RISC-V AIA drivers

Message ID	20230710094321.1378351-10-apatel@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Conor Dooley <conor@kernel.org>, Saravana Kannan <saravanak@google.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v5 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Date: Mon, 10 Jul 2023 15:13:21 +0530 Message-Id: <20230710094321.1378351-10-apatel@ventanamicro.com> In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Linux RISC-V AIA Support \| [v5,0/9] Linux RISC-V AIA Support [v5,1/9] RISC-V: Add riscv_fw_parent_hartid() function [v5,2/9] irqchip/riscv-intc: Add support for RISC-V AIA [v5,3/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller [v5,4/9] irqchip: Add RISC-V incoming MSI controller driver [v5,5/9] irqchip/riscv-imsic: Add support for PCI MSI irqdomain [v5,6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC [v5,7/9] irqchip: Add RISC-V advanced PLIC driver [v5,8/9] RISC-V: Select APLIC and IMSIC drivers [v5,9/9] MAINTAINERS: Add entry for RISC-V AIA drivers

Commit Message

Anup Patel July 10, 2023, 9:43 a.m. UTC

  Add myself as maintainer for RISC-V AIA drivers including the
RISC-V INTC driver which supports both AIA and non-AIA platforms.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 MAINTAINERS | 12 ++++++++++++
 1 file changed, 12 insertions(+)

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Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 3be1bdfe8ecc..a85fc0102179 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18245,6 +18245,18 @@  S:	Maintained
 F:	drivers/mtd/nand/raw/r852.c
 F:	drivers/mtd/nand/raw/r852.h
 
+RISC-V AIA DRIVERS
+M:	Anup Patel <anup@brainfault.org>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+F:	drivers/irqchip/irq-riscv-aplic.c
+F:	drivers/irqchip/irq-riscv-imsic.c
+F:	drivers/irqchip/irq-riscv-intc.c
+F:	include/linux/irqchip/riscv-aplic.h
+F:	include/linux/irqchip/riscv-imsic.h
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>