Message ID | 20230706105045.633076-5-quic_imrashai@quicinc.com |
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State | New |
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Thu, 06 Jul 2023 10:51:57 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 366Apunm015420 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 6 Jul 2023 10:51:56 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 6 Jul 2023 03:51:51 -0700 From: Imran Shaik <quic_imrashai@quicinc.com> To: Andy Gross <agross@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: Bjorn Andersson <andersson@kernel.org>, Taniya Das <quic_tdas@quicinc.com>, Imran Shaik <quic_imrashai@quicinc.com>, "Melody Olvera" <quic_molvera@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Jagadeesh Kona <quic_jkona@quicinc.com>, Satya Priya Kakitapalli <quic_skakitap@quicinc.com>, Ajit Pandey <quic_ajipan@quicinc.com> Subject: [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version Date: Thu, 6 Jul 2023 16:20:43 +0530 Message-ID: <20230706105045.633076-5-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230706105045.633076-1-quic_imrashai@quicinc.com> References: <20230706105045.633076-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fLO8rgX1uCojQJ9RYWFCOlePWCkakgQC X-Proofpoint-ORIG-GUID: fLO8rgX1uCojQJ9RYWFCOlePWCkakgQC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-06_07,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307060095 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770669296235641025?= X-GMAIL-MSGID: =?utf-8?q?1770669296235641025?= |
Series |
Update GCC clocks for QDU1000 and QRU1000 SoCs
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Commit Message
Imran Shaik
July 6, 2023, 10:50 a.m. UTC
Update the GCC clocks as per the latest hw version of QDU1000 and QRU100 SoCs. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> --- Changes since v2: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
Comments
On 6.07.2023 12:50, Imran Shaik wrote: > Update the GCC clocks as per the latest hw version of QDU1000 and > QRU100 SoCs. > > Co-developed-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > --- > Changes since v2: > - Split the patch as per the review comments > - Newly added > > drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c > index 8df7b7983968..991fb2bc97e9 100644 > --- a/drivers/clk/qcom/gcc-qdu1000.c > +++ b/drivers/clk/qcom/gcc-qdu1000.c > @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { > }, > }; > > +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { > + .halt_reg = 0x54298, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x54298, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x54298, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_ddrss_ecpri_gsi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_ecpri_ahb_clk = { > .halt_reg = 0x3a008, > .halt_check = BRANCH_HALT_VOTED, > @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { > [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, > [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, > [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, > + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, Looks like you split it too much.. this clock is not being defined in this patch. Konrad > + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, > }; > > static const struct qcom_reset_map gcc_qdu1000_resets[] = {
On 7/15/2023 6:50 PM, Konrad Dybcio wrote: > On 6.07.2023 12:50, Imran Shaik wrote: >> Update the GCC clocks as per the latest hw version of QDU1000 and >> QRU100 SoCs. >> >> Co-developed-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> >> --- >> Changes since v2: >> - Split the patch as per the review comments >> - Newly added >> >> drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c >> index 8df7b7983968..991fb2bc97e9 100644 >> --- a/drivers/clk/qcom/gcc-qdu1000.c >> +++ b/drivers/clk/qcom/gcc-qdu1000.c >> @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { >> }, >> }; >> >> +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { >> + .halt_reg = 0x54298, >> + .halt_check = BRANCH_HALT_VOTED, >> + .hwcg_reg = 0x54298, >> + .hwcg_bit = 1, >> + .clkr = { >> + .enable_reg = 0x54298, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ddrss_ecpri_gsi_clk", >> + .parent_hws = (const struct clk_hw*[]) { >> + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_aon_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_ecpri_ahb_clk = { >> .halt_reg = 0x3a008, >> .halt_check = BRANCH_HALT_VOTED, >> @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { >> [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, >> [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, >> [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, >> + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, > Looks like you split it too much.. this clock is not being defined in this patch. > > Konrad This clock was already defined in the initial gcc changes and now adding it to gcc_qdu1000_clocks[] to register it with the clock framework. Thanks, Imran >> + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, >> }; >> >> static const struct qcom_reset_map gcc_qdu1000_resets[] = {
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 8df7b7983968..991fb2bc97e9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = {