[V2,2/2] arm64: dts: add board AN400
Commit Message
Add devicetrees support for Amlogic AN400 board based T7 SoC.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
V1 -> V2: fix bug when use "DTC CHECK_DTBS=yes"
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../dts/amlogic/amlogic-t7-a311d2-an400.dts | 39 +++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
+dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb
new file mode 100644
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "amlogic-t7.dtsi"
+
+/ {
+ model = "Amlogic A311D2 AN400 Development Board";
+ compatible = "amlogic,an400", "amlogic,a311d2", "amlogic,t7";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_a;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0xE0000000
+ 0x00000001 0x00000000 0x00000000 0x20000000>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+};
+
+&uart_a {
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "okay";
+};