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Signed-off-by: Charlie Jenkins --- Documentation/riscv/hwprobe.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 19165ebd82ba..167fd3e25632 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -97,3 +97,20 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are not supported at all and will generate a misaligned address fault. + +RISC-V Hardware Probing Interface Vendor Extensions +--------------------------------------------------- + +All vendor extensions live at and beyond +:c:macro:`RISCV_HWPROBE_VENDOR_EXTENSION_SPACE`. Each vendor can specify vendor +extensions at any value above or equal to +:c:macro:`RISCV_HWPROBE_VENDOR_EXTENSION_SPACE` without worrying about +conflicting with values from other vendors. Only extensions from the vendor of +the cpus passed into riscv_hwprobe will be matched. + +T-HEAD +~~~~~~ + +* :c:macro:`THEAD_ISA_EXT0`: Contains all of the EXT0 extensions + + * :c:macro:`THEAD_ISA_EXT0_V0_7_1`: Vector extension V0.7.1 is supported