Message ID | 20230704092200.85401-2-william.qiu@starfivetech.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l184-20020a6388c1000000b0054481da6ee5si20031570pgd.418.2023.07.04.02.34.57; Tue, 04 Jul 2023 02:35:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232089AbjGDJWf convert rfc822-to-8bit (ORCPT <rfc822;ybw1215001957@gmail.com> + 99 others); Tue, 4 Jul 2023 05:22:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231978AbjGDJWL (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 4 Jul 2023 05:22:11 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6302010E5; Tue, 4 Jul 2023 02:22:04 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BCDB0828C; Tue, 4 Jul 2023 17:22:02 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:22:02 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 17:22:01 +0800 From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> CC: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Linus Walleij <linus.walleij@linaro.org>, William Qiu <william.qiu@starfivetech.com> Subject: [RESEND v1 1/2] dt-binding: spi: constrain minItems of clocks and clock-names Date: Tue, 4 Jul 2023 17:21:59 +0800 Message-ID: <20230704092200.85401-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704092200.85401-1-william.qiu@starfivetech.com> References: <20230704092200.85401-1-william.qiu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770482103879114774?= X-GMAIL-MSGID: =?utf-8?q?1770482103879114774?= |
Series |
Add SPI module for StarFive JH7110 SoC
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Commit Message
William Qiu
July 4, 2023, 9:21 a.m. UTC
The SPI controller only need apb_pclk clock to work properly on JH7110 SoC,
so there add minItems whose value is equal to 1. Other platforms do not
have this constraint.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
--
2.34.1
Comments
On 04/07/2023 11:21, William Qiu wrote: > The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, > so there add minItems whose value is equal to 1. Other platforms do not > have this constraint. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> I don't get why this is resent, but subject prefix is still wrong. It's dt-bindings. > --- > Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml > index 91e540a92faf..42bb34c39971 100644 > --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml > @@ -11,6 +11,7 @@ maintainers: > > allOf: > - $ref: spi-controller.yaml# > + - $ref: /schemas/arm/primecell.yaml# This looks unrelated, so keep it as separate commit with its own rationale. > > # We need a select here so we don't match all nodes with 'arm,primecell' > select: > @@ -34,12 +35,16 @@ properties: > maxItems: 1 > > clocks: > + minItems: 1 > maxItems: 2 > > clock-names: > - items: > - - const: sspclk > - - const: apb_pclk > + oneOf: > + - items: > + - const: apb_pclk > + - items: > + - const: sspclk > + - const: apb_pclk Are you sure that your clock is APB pclk in such case? Best regards, Krzysztof
On 2023/7/4 17:38, Krzysztof Kozlowski wrote: > On 04/07/2023 11:21, William Qiu wrote: >> The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, >> so there add minItems whose value is equal to 1. Other platforms do not >> have this constraint. >> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com> > > I don't get why this is resent, but subject prefix is still wrong. It's > dt-bindings. > Will update. >> --- >> Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- >> 1 file changed, 8 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >> index 91e540a92faf..42bb34c39971 100644 >> --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml >> +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >> @@ -11,6 +11,7 @@ maintainers: >> >> allOf: >> - $ref: spi-controller.yaml# >> + - $ref: /schemas/arm/primecell.yaml# > > This looks unrelated, so keep it as separate commit with its own rationale. > Because "arm,primecell-periphid" is need in JH7110 SoC, so I added them in one commit, so do I need to put them in two commit? >> >> # We need a select here so we don't match all nodes with 'arm,primecell' >> select: >> @@ -34,12 +35,16 @@ properties: >> maxItems: 1 >> >> clocks: >> + minItems: 1 >> maxItems: 2 >> >> clock-names: >> - items: >> - - const: sspclk >> - - const: apb_pclk >> + oneOf: >> + - items: >> + - const: apb_pclk >> + - items: >> + - const: sspclk >> + - const: apb_pclk > > Are you sure that your clock is APB pclk in such case? > Yes, in JH7110 SoC is APB pclk in such case. Thanks for taking time to review this patch series. > Best regards, > Krzysztof >
On 05/07/2023 05:37, William Qiu wrote: >>> --- >>> Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- >>> 1 file changed, 8 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>> index 91e540a92faf..42bb34c39971 100644 >>> --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>> +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>> @@ -11,6 +11,7 @@ maintainers: >>> >>> allOf: >>> - $ref: spi-controller.yaml# >>> + - $ref: /schemas/arm/primecell.yaml# >> >> This looks unrelated, so keep it as separate commit with its own rationale. >> > Because "arm,primecell-periphid" is need in JH7110 SoC, so I added them in > one commit, so do I need to put them in two commit? You need to provide rationale why this is needed. I would assume this is needed for every primecell, not only JH7110, right? Best regards, Krzysztof
On 2023/7/5 14:00, Krzysztof Kozlowski wrote: > On 05/07/2023 05:37, William Qiu wrote: >>>> --- >>>> Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- >>>> 1 file changed, 8 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>>> index 91e540a92faf..42bb34c39971 100644 >>>> --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>>> +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml >>>> @@ -11,6 +11,7 @@ maintainers: >>>> >>>> allOf: >>>> - $ref: spi-controller.yaml# >>>> + - $ref: /schemas/arm/primecell.yaml# >>> >>> This looks unrelated, so keep it as separate commit with its own rationale. >>> >> Because "arm,primecell-periphid" is need in JH7110 SoC, so I added them in >> one commit, so do I need to put them in two commit? > > You need to provide rationale why this is needed. I would assume this is > needed for every primecell, not only JH7110, right? > > All right, I'll keep it as separate commit. > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml index 91e540a92faf..42bb34c39971 100644 --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: @@ -34,12 +35,16 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 2 clock-names: - items: - - const: sspclk - - const: apb_pclk + oneOf: + - items: + - const: apb_pclk + - items: + - const: sspclk + - const: apb_pclk pl022,autosuspend-delay: description: delay in ms following transfer completion before the