From patchwork Tue Jul 4 06:46:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 115580 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1023175vqx; Tue, 4 Jul 2023 00:01:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4BYdRJ0avxO4u9ZOsiKA288K6WtWd7M1xWLKTb+In3l9Jfskmay9pPBIDM0bD/tWhAlBNl X-Received: by 2002:a05:6870:1e83:b0:1b0:12d7:1ef6 with SMTP id pb3-20020a0568701e8300b001b012d71ef6mr13716136oab.25.1688454072431; Tue, 04 Jul 2023 00:01:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688454072; cv=none; d=google.com; s=arc-20160816; b=UifvjjR0n1phqGZ4orjbUa5qeHpZkwl02PhJHNWwu7w61dNYXw2vvI2qEY7Q4nNV8/ W3qZgWdhKUhJvOpd1RdtjzPj8T0k46MKptHepVYqz8qKit5RNzWnCQIgaUL4MDk0y1o1 gKQo66hwA8wzZN03DC4taA3sGBT9Btmo1AVA/Lbb9vll2YYDGOx9eq7fQrWx2VFFtuIR W/bmannOZ0NBeTIfTGNNgJlK+hzaQE0G+Ogo7ejydzYgxjhjDAjPsS28sLcCvYy/5Iqt ypLvE3/H8wHdNindaKBk/cZ9tKqLNOuwV0QjZcr5aseE7lLXAldFOBCoCXnkjqZhgOKL IpDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eX8TJ48WrpN9T1o8dEU5rDQ8g65ALcZ9/uM7306XLrw=; fh=bO0lyCpGdMRsyk4A5AR7qGoLpbBaIJeTbIlSNG9VSf0=; b=HwFcl1BMN581x5qOx4QqWk2Um0P2+wPaoz7/vP2ar+Dl2UmyY7Q/i0WBS7fCoJV/1W jLqnEeiQk3yCIoDVoEI0k46OG3uM0TbM89Ne3jBZXBRRqOKCoSERQ7+k4BxiiPq9Yuzq epi0MNYvCtO1nKQRsdYvYV44jZJ2yX0ytPIbGicoDhDvxoZghje+keJ+8NwuqnzFh9Yi +EZstkrl+cL3QX0QaBZtxyu7wym+RCgWbV4WtbXTEfrW8KbCaNJDXOeUr+2niiflSOXJ CWD8npYJJuOkSxX9rSsKp8l/a2EmkXqqmmm4JYL1LJoqDkDiNOucXlWYHalfCrs+w3rt 1RzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j11-20020a17090a318b00b0026122e09522si19649451pjb.56.2023.07.04.00.00.55; Tue, 04 Jul 2023 00:01:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbjGDGtv convert rfc822-to-8bit (ORCPT + 99 others); Tue, 4 Jul 2023 02:49:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230426AbjGDGt3 (ORCPT ); Tue, 4 Jul 2023 02:49:29 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 442B610CB; Mon, 3 Jul 2023 23:49:18 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id A7211814B; Tue, 4 Jul 2023 14:49:16 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 14:49:16 +0800 Received: from localhost.localdomain (113.72.144.31) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 4 Jul 2023 14:49:15 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , "William Qiu" , , Subject: [RESEND PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Date: Tue, 4 Jul 2023 14:46:04 +0800 Message-ID: <20230704064610.292603-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230704064610.292603-1-xingyu.wu@starfivetech.com> References: <20230704064610.292603-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.31] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770472417825447519?= X-GMAIL-MSGID: =?utf-8?q?1770472417825447519?= Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu --- .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..beb78add5a8d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + These PLLs are high speed, low jitter frequency synthesizers in JH7110. + Each PLL works in integer mode or fraction mode, with configuration + registers in the sys syscon. So the PLLs node should be a child of + SYS-SYSCON node. + The formula for calculating frequency is + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..086a6ddcf380 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -6,6 +6,12 @@ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_CLK_PLL0_OUT 0 +#define JH7110_CLK_PLL1_OUT 1 +#define JH7110_CLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1