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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 33-20020a630a21000000b0054fd06a3585si12286458pgk.158.2023.06.30.08.27.10; Fri, 30 Jun 2023 08:27:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=NWJ3UXef; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232563AbjF3PQH (ORCPT + 99 others); Fri, 30 Jun 2023 11:16:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232988AbjF3PPi (ORCPT ); Fri, 30 Jun 2023 11:15:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FA734223; Fri, 30 Jun 2023 08:15:12 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 140A26606E8F; Fri, 30 Jun 2023 16:15:07 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138111; bh=dDGAXyQUfLadYEQWCBPnnvjplu6XpXRhFI0R4wZeknQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NWJ3UXefi7IM8PfvLotte4aH7+mfmG6/EOg0Hw3Xrk6BgVNewtTzHG+1im3xgDRzc JRRurXszbqn69mie2NVsb7BfeEkyBwcLLoRBjDMGc2rSUu1PnSgn3yOIAqcDe/bwIn /ATUETo8Vr/cPlLffwXuMYO/cw2DUm7XGrZnMNP8+eB3maxXYr5SurRkD3Sx2TLxts fVIRv7U6OaTOLo8UeowbsW6K2KmVR5AlxnvrBsgcb/PtNfdvuhaGsgKmNL89bvos2+ Jxb5KewPGoT9LgMfEnHxCs1kHxd1kKVs7vXanx5KhZ2lqryEBlad5zGCoYPv/B/TwJ 48sNRg+K+apgQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Yunfei Dong , =?utf-8?q?N?= =?utf-8?q?=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 7/7] arm64: dts: mediatek: mt8183: Add decoder Date: Fri, 30 Jun 2023 11:14:13 -0400 Message-ID: <20230630151436.155586-8-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770141875740547426?= X-GMAIL-MSGID: =?utf-8?q?1770141875740547426?= From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: - Dropped 'active' clock and added the 'mediatek,vdecsys' syscon phandle property instead Changes in v2: - Reformatted reg-names to fit in fewer lines arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..4144f1ed3ff0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,36 @@ vdecsys: syscon@16000000 { #clock-cells = <1>; }; + vcodec_dec: video-codec@16020000 { + compatible = "mediatek,mt8183-vcodec-dec"; + reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp", + "hwd", "hwq", "hwb", "hwg"; + interrupts = ; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp = <&scp>; + mediatek,vdecsys = <&vdecsys>; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_VDEC>; + clock-names = "vdec"; + }; + larb1: larb@16010000 { compatible = "mediatek,mt8183-smi-larb"; reg = <0 0x16010000 0 0x1000>;