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[2620:137:e000::1:20]) by mx.google.com with ESMTP id np17-20020a17090b4c5100b0025bea0a396asi14072295pjb.6.2023.06.29.02.14.40; Thu, 29 Jun 2023 02:14:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=sT0AOZM5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232553AbjF2IbO (ORCPT + 99 others); Thu, 29 Jun 2023 04:31:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232630AbjF2IaL (ORCPT ); Thu, 29 Jun 2023 04:30:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6F15268F; Thu, 29 Jun 2023 01:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027408; x=1719563408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HPRtOyIqm/BcHFGgw0cl0PQB3rNvTkemYLiSjsKMtC8=; b=sT0AOZM5Pjboy+PjBFw3Fli4cBuimhYwGucWRwZYKQmrsV/vQAww2LpG A6grQARV7+1POOyM4nQpRKjWtfm+UG4XKdenNFQxJUrVYRwpGC80CbP6H kCyxiEaGNFtTJt9dqnFdpHvzFRTqFSDf4k7n93rinZsZdlAH3ADt9h56p SQXuJVP3GIrWa9iMW4vm4uWIH1jjH2llrTHe1f+4eTXkET7YaN9LHmxXC 2KuzmCLvlmvXgIixP9C0P02oU51cfz7KO4TgwiuEVWhHJeMJPM85UmniZ M1gMbofUgVBlhA3848woQxw5HQMnOthxvp2klMPnTKp5TfbFUSR80eGfK g==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="221156087" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:00 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:58 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 05/10] RISC-V: add missing single letter extension definitions Date: Thu, 29 Jun 2023 09:28:51 +0100 Message-ID: <20230629-disengage-cornbread-3876ec5b9e96@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1204; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=HPRtOyIqm/BcHFGgw0cl0PQB3rNvTkemYLiSjsKMtC8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ7l626WmZpff9hgpUqIwsNvnc17glU4/tntZbpiHPBh YvKNjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzksg0jw2WVLce/L9aw9RHdfex1V2 rOlk/Tz/k+WP1ztVFgodn540AVz840NX8qvsLX+sm97Faa3GYfTTaxRBXutvvbRC/PWDuZFQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770027842818960300?= X-GMAIL-MSGID: =?utf-8?q?1770027842818960300?= To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2460ac2fc7ed..a20e4ade1b53 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a')