Message ID | 20230627-sm6125-dpu-v2-13-03e430a2078c@somainline.org |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp8462377vqr; Tue, 27 Jun 2023 13:49:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6o1s8ZZOmRKkLq/nzx9Y3R2k+tcLRP1oaQ0+4jZ4KGtgQ3ku5MGHgQO8SCyh1vKmhxZEVt X-Received: by 2002:a05:6402:3481:b0:51b:cb81:ca19 with SMTP id v1-20020a056402348100b0051bcb81ca19mr21552706edc.8.1687898951145; Tue, 27 Jun 2023 13:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687898951; cv=none; d=google.com; s=arc-20160816; b=u/nR7ckWl8Ds4vB0b+kgYimYg+lB2YGXbLEbJUNtAsG1u/8QVxXRJZw8leYDUt4uQk 2+/ppuMkYCXGv/HUzaCGk9mgpyEvPPFP1yji4eaDWoy7eEviLjMjTW3Dhnx6uTLTnN0f sIajhkmxkIf7qOyjjjfGTf8OogMgUN+zYGobwwNwvYNWCpkVbZnz4o0MV9Ak1twAI1fz 84O2b73cDOjn6+dQ5tGINEMGal5ZlugS3XhieEgjW4/QU+wvaF0ghVtCOmALXfBqWs8u 8BIXvEi1UogGMBmmt5cN0Y2I5XmMWces/g8GqplmNQwat1xtSyqfJn4ekMzN+63DuZ3f jkXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=uljMcjHMsqSLl/cmzi/dT33P+x4MPUwaGsLtaAKLk/4=; fh=pj9lVTD7zJGSjaLEKdvLb7dkz1RbGKHUxYpQTxVQ54Y=; b=rjTzcAoWmWnfTm8+RfgbHRCS/4H9rlf0SOwelyWSR7OPB5/+2CqpgGnrdzacNkubgM AvGD0uhgaRgbG0fuuVtU3W0BpAv1jWKw04/n46z4ZkVTSJD2yyWxIdIyZSpIjqpfcJHE CcTh69K1cSniBinmwofz8DCgMVHTJVwyefgT7NhWElFAOYT2f31tpQ6+6bAOJupZGvsw 0bdtEiTux+qdjCH4N7lTokt4SL7o3DdpFSNFnzrYB9sk8/4wyae/0DjMOasvLD996Lir IIVRhNZVsOhMOhWbPeJJJWD2WC5uZWs+CaKmc4MxTlBAeuMJq46It9OrEOCmObN0cnLk frow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n10-20020aa7c78a000000b0051bf671a7fasi4189489eds.577.2023.06.27.13.48.46; Tue, 27 Jun 2023 13:49:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231620AbjF0UPp (ORCPT <rfc822;nicolai.engesland@gmail.com> + 99 others); Tue, 27 Jun 2023 16:15:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbjF0UOq (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 27 Jun 2023 16:14:46 -0400 Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF1052D50; Tue, 27 Jun 2023 13:14:41 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id A7DB33F751; Tue, 27 Jun 2023 22:14:38 +0200 (CEST) From: Marijn Suijten <marijn.suijten@somainline.org> Date: Tue, 27 Jun 2023 22:14:28 +0200 Subject: [PATCH v2 13/15] arm64: dts: qcom: sm6125: Add dispcc node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230627-sm6125-dpu-v2-13-03e430a2078c@somainline.org> References: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> In-Reply-To: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Krishna Manikandan <quic_mkrishn@quicinc.com>, Marijn Suijten <marijn.suijten@somainline.org>, Loic Poulain <loic.poulain@linaro.org>, Konrad Dybcio <konrad.dybcio@somainline.org> Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Konrad Dybcio <konrad.dybcio@linaro.org>, Martin Botka <martin.botka@somainline.org>, Jami Kettunen <jami.kettunen@somainline.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga <they@mint.lgbt> X-Mailer: b4 0.12.3 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769890330604074318?= X-GMAIL-MSGID: =?utf-8?q?1769890330604074318?= |
Series |
drm/msm: Add SM6125 MDSS/DPU hardware and enable Sony Xperia 10 II panel
|
|
Commit Message
Marijn Suijten
June 27, 2023, 8:14 p.m. UTC
Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
Comments
On 27/06/2023 23:14, Marijn Suijten wrote: > Enable and configure the dispcc node on SM6125 for consumption by MDSS > later on. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index edb03508dba3..a5cc0d43d2d9 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -1203,6 +1204,30 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > > + dispcc: clock-controller@5f00000 { > + compatible = "qcom,sm6125-dispcc"; > + reg = <0x05f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk", > + "cfg_ahb_clk", > + "gcc_disp_gpll0_div_clk_src"; > + power-domains = <&rpmpd SM6125_VDDCX>; Would it be logical to specify the required-opps too? > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > apps_smmu: iommu@c600000 { > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0c600000 0x80000>; >
On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: > On 27/06/2023 23:14, Marijn Suijten wrote: > > Enable and configure the dispcc node on SM6125 for consumption by MDSS > > later on. > > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > index edb03508dba3..a5cc0d43d2d9 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > > */ > > > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > > #include <dt-bindings/clock/qcom,rpmcc.h> > > #include <dt-bindings/dma/qcom-gpi.h> > > @@ -1203,6 +1204,30 @@ sram@4690000 { > > reg = <0x04690000 0x10000>; > > }; > > > > + dispcc: clock-controller@5f00000 { > > + compatible = "qcom,sm6125-dispcc"; > > + reg = <0x05f00000 0x20000>; > > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > > + <0>, > > + <0>, > > + <0>, > > + <0>, > > + <0>, > > + <&gcc GCC_DISP_AHB_CLK>, > > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > > + clock-names = "bi_tcxo", > > + "dsi0_phy_pll_out_byteclk", > > + "dsi0_phy_pll_out_dsiclk", > > + "dsi1_phy_pll_out_dsiclk", > > + "dp_phy_pll_link_clk", > > + "dp_phy_pll_vco_div_clk", > > + "cfg_ahb_clk", > > + "gcc_disp_gpll0_div_clk_src"; > > + power-domains = <&rpmpd SM6125_VDDCX>; > > Would it be logical to specify the required-opps too? Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI PHY despite not having a reference value downstream (it sets a range of NOM-TURBO_NO_CPR, and RETENTION when it's off). - Marijn > > > + #clock-cells = <1>; > > + #power-domain-cells = <1>; > > + }; > > + > > apps_smmu: iommu@c600000 { > > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > > reg = <0x0c600000 0x80000>; > > > > -- > With best wishes > Dmitry >
On Thu, 29 Jun 2023 at 15:14, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: > > On 27/06/2023 23:14, Marijn Suijten wrote: > > > Enable and configure the dispcc node on SM6125 for consumption by MDSS > > > later on. > > > > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > > --- > > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > > > 1 file changed, 25 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > index edb03508dba3..a5cc0d43d2d9 100644 > > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > @@ -3,6 +3,7 @@ > > > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > > > */ > > > > > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > > > #include <dt-bindings/clock/qcom,rpmcc.h> > > > #include <dt-bindings/dma/qcom-gpi.h> > > > @@ -1203,6 +1204,30 @@ sram@4690000 { > > > reg = <0x04690000 0x10000>; > > > }; > > > > > > + dispcc: clock-controller@5f00000 { > > > + compatible = "qcom,sm6125-dispcc"; > > > + reg = <0x05f00000 0x20000>; > > > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <&gcc GCC_DISP_AHB_CLK>, > > > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > > > + clock-names = "bi_tcxo", > > > + "dsi0_phy_pll_out_byteclk", > > > + "dsi0_phy_pll_out_dsiclk", > > > + "dsi1_phy_pll_out_dsiclk", > > > + "dp_phy_pll_link_clk", > > > + "dp_phy_pll_vco_div_clk", > > > + "cfg_ahb_clk", > > > + "gcc_disp_gpll0_div_clk_src"; > > > + power-domains = <&rpmpd SM6125_VDDCX>; > > > > Would it be logical to specify the required-opps too? > > Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. > What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI > PHY despite not having a reference value downstream (it sets a range of > NOM-TURBO_NO_CPR, and RETENTION when it's off). Then for DSI PHY the required-opps should be rpmpd_opp_nom. For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, should be enough. > > - Marijn > > > > > > + #clock-cells = <1>; > > > + #power-domain-cells = <1>; > > > + }; > > > + > > > apps_smmu: iommu@c600000 { > > > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > > > reg = <0x0c600000 0x80000>; > > > > > > > -- > > With best wishes > > Dmitry > >
On 29.06.2023 14:24, Dmitry Baryshkov wrote: > On Thu, 29 Jun 2023 at 15:14, Marijn Suijten > <marijn.suijten@somainline.org> wrote: >> >> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: >>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS >>>> later on. >>>> >>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ >>>> 1 file changed, 25 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> index edb03508dba3..a5cc0d43d2d9 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> @@ -3,6 +3,7 @@ >>>> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> >>>> */ >>>> >>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,rpmcc.h> >>>> #include <dt-bindings/dma/qcom-gpi.h> >>>> @@ -1203,6 +1204,30 @@ sram@4690000 { >>>> reg = <0x04690000 0x10000>; >>>> }; >>>> >>>> + dispcc: clock-controller@5f00000 { >>>> + compatible = "qcom,sm6125-dispcc"; >>>> + reg = <0x05f00000 0x20000>; >>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <&gcc GCC_DISP_AHB_CLK>, >>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >>>> + clock-names = "bi_tcxo", >>>> + "dsi0_phy_pll_out_byteclk", >>>> + "dsi0_phy_pll_out_dsiclk", >>>> + "dsi1_phy_pll_out_dsiclk", >>>> + "dp_phy_pll_link_clk", >>>> + "dp_phy_pll_vco_div_clk", >>>> + "cfg_ahb_clk", >>>> + "gcc_disp_gpll0_div_clk_src"; >>>> + power-domains = <&rpmpd SM6125_VDDCX>; >>> >>> Would it be logical to specify the required-opps too? >> >> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. >> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI >> PHY despite not having a reference value downstream (it sets a range of >> NOM-TURBO_NO_CPR, and RETENTION when it's off). > > Then for DSI PHY the required-opps should be rpmpd_opp_nom. Yes > > For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, > should be enough. I'm not 100% sure but not specifying an opp and turning on the domain *******probably******* just sticks with the lowest vote Konrad > >> >> - Marijn >> >>> >>>> + #clock-cells = <1>; >>>> + #power-domain-cells = <1>; >>>> + }; >>>> + >>>> apps_smmu: iommu@c600000 { >>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>> reg = <0x0c600000 0x80000>; >>>> >>> >>> -- >>> With best wishes >>> Dmitry >>> > > >
On 29/06/2023 22:53, Konrad Dybcio wrote: > On 29.06.2023 14:24, Dmitry Baryshkov wrote: >> On Thu, 29 Jun 2023 at 15:14, Marijn Suijten >> <marijn.suijten@somainline.org> wrote: >>> >>> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: >>>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS >>>>> later on. >>>>> >>>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ >>>>> 1 file changed, 25 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> index edb03508dba3..a5cc0d43d2d9 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> @@ -3,6 +3,7 @@ >>>>> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> >>>>> */ >>>>> >>>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >>>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >>>>> #include <dt-bindings/clock/qcom,rpmcc.h> >>>>> #include <dt-bindings/dma/qcom-gpi.h> >>>>> @@ -1203,6 +1204,30 @@ sram@4690000 { >>>>> reg = <0x04690000 0x10000>; >>>>> }; >>>>> >>>>> + dispcc: clock-controller@5f00000 { >>>>> + compatible = "qcom,sm6125-dispcc"; >>>>> + reg = <0x05f00000 0x20000>; >>>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <&gcc GCC_DISP_AHB_CLK>, >>>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >>>>> + clock-names = "bi_tcxo", >>>>> + "dsi0_phy_pll_out_byteclk", >>>>> + "dsi0_phy_pll_out_dsiclk", >>>>> + "dsi1_phy_pll_out_dsiclk", >>>>> + "dp_phy_pll_link_clk", >>>>> + "dp_phy_pll_vco_div_clk", >>>>> + "cfg_ahb_clk", >>>>> + "gcc_disp_gpll0_div_clk_src"; >>>>> + power-domains = <&rpmpd SM6125_VDDCX>; >>>> >>>> Would it be logical to specify the required-opps too? >>> >>> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. >>> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI >>> PHY despite not having a reference value downstream (it sets a range of >>> NOM-TURBO_NO_CPR, and RETENTION when it's off). >> >> Then for DSI PHY the required-opps should be rpmpd_opp_nom. > Yes > >> >> For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, >> should be enough. > I'm not 100% sure but not specifying an opp and turning on the domain > *******probably******* just sticks with the lowest vote I think so too. But I think it might be better to be explicit rather than being implicit here. Both of us are describing Linux behaviour (=set lowest possible value), while DT should describe the hardware. > > Konrad >> >>> >>> - Marijn >>> >>>> >>>>> + #clock-cells = <1>; >>>>> + #power-domain-cells = <1>; >>>>> + }; >>>>> + >>>>> apps_smmu: iommu@c600000 { >>>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>>> reg = <0x0c600000 0x80000>; >>>>> >>>> >>>> -- >>>> With best wishes >>>> Dmitry >>>> >> >> >>
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index edb03508dba3..a5cc0d43d2d9 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> */ +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -1203,6 +1204,30 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,sm6125-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "cfg_ahb_clk", + "gcc_disp_gpll0_div_clk_src"; + power-domains = <&rpmpd SM6125_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>;