From patchwork Mon Jun 26 09:52:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 112836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7380278vqr; Mon, 26 Jun 2023 03:32:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4hzm4+EVkQ6kNZDWmr1ynC0+km40LpdvsQXLmu0Bra0qyOVZ5NwkLcj6vdU5pUIfhRuMdr X-Received: by 2002:a17:907:160d:b0:989:4776:11a1 with SMTP id hb13-20020a170907160d00b00989477611a1mr14800697ejc.47.1687775569043; Mon, 26 Jun 2023 03:32:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687775569; cv=none; d=google.com; s=arc-20160816; b=AYpG2LZLsmgcYF8DOjZKPDkL0qVWKggxqiUn7Ke3WUf1E6Mk26Rg2MHJ5cYhfWt666 +tyMcO2zGHVLH6xZYE4bVw4E1BhZ4KJs1FQPMKQaABRtYm/5+GRbRYGbpvMsMZ3zB6Ie BHqpKRx+ryv15v6cDgKywl8EPmlDJYuZ50369lfPHOnYP+uR04i7jx8C7Bg8DFt93kzY 8MYkFXfHQMks0aCcA6c6uZqpnJ+ukoTpgtPBXOCfsT9hE931L/cniSsuZ4fYhvVg5xz9 HK6dcmx/Nnhag75870W25JqnWxpIhPDOG03ogpcT6oMmAw+RzyQLA7n/Muej1qkYPB4y nrDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=v53jinPjpouCrMRq2OtHJABF1okDvarM5vdozO6I36Q=; fh=fDu4phjj3Kd5v9eUQrOXvEpWfoeaojR6TUARK8xL7Uo=; b=n84HNhBe9dBzBxZDvNIqpJM2YrGYDHCFquXsQ1TxOac4gwoZTurQaQmA7nRCu5RCu9 1ZZGA1MeDISWkbczIIW/NOzne/o1NfrHP1V4LT4qx26j0DksfsBrpEt7IkmQ/uT66x1P 5VKPK17ZoCeRkKM+lEVQMmAMfLVtZLe4lxQiCrYpov3vTYDX7qQ5L8/6QtIcdmb8Gmbh XxJWzWBo/kwFyGoFRgrJZ0yt7PaPswWQJ2bM5kae7rsQe5xM4K0G5u+nhp62+MPzFbg+ xNFYVj4w5oCEowmU0M0qfwBprr7WNvGYzIrZSaIvlzW53h1izTN/S/a9HpbOQCkqaVhK DWCQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t7-20020a17090616c700b0098cf69d9447si2400112ejd.820.2023.06.26.03.32.25; Mon, 26 Jun 2023 03:32:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbjFZJxW (ORCPT + 99 others); Mon, 26 Jun 2023 05:53:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230249AbjFZJxU (ORCPT ); Mon, 26 Jun 2023 05:53:20 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 800829B; Mon, 26 Jun 2023 02:52:32 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 26 Jun 2023 17:52:29 +0800 From: Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Xianwei Zhao Subject: [PATCH 2/2] arm64: dts: add support for T7 based Amlogic AN400 Date: Mon, 26 Jun 2023 17:52:23 +0800 Message-ID: <20230626095223.721011-3-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230626095223.721011-1-xianwei.zhao@amlogic.com> References: <20230626095223.721011-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769760955081914023?= X-GMAIL-MSGID: =?utf-8?q?1769760955081914023?= Amlogic T7 is an advanced application processor designed for smart display. Add basic support for the T7 based Amlogic AN400 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/amlogic-t7-a311d2-an400.dts | 30 ++++ arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 156 ++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 6f61798a109f..99299731f5d4 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts new file mode 100644 index 000000000000..7ce1975b99e4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-t7.dtsi" + +/ { + model = "Amlogic A311D2 AN400 Development Board"; + compatible = "amlogic,an400", "amlogic,t7"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_a; + }; + + memory@0 { + device_type = "memory"; + linux,usable-memory = <0x00000000 0x00000000 0x00000000 0xE0000000 + 0x00000001 0x00000000 0x00000000 0x20000000>; + }; +}; + +&uart_a { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi new file mode 100644 index 000000000000..d3ee864f0d40 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +/ { + cpus:cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2:cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3:cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + cpu4:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu5:cpu@101{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu6:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu7:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x0100>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_a: serial@78000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x78000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>,<&xtal>,<&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + }; +};