diff mbox series

[08/10] arm64: dts: imx8ulp-evk: add spi-nor device support

Message ID 20230625124238.4071717-9-peng.fan@oss.nxp.com
State New
Headers
Series arm64: dts: imx8ulp: add more nodes |

Commit Message

Peng Fan (OSS) June 25, 2023, 12:42 p.m. UTC 
  From: Han Xu <han.xu@nxp.com>

Add spi-nor support.
- 8 bit mode for RX/TX.
- Set the clock rate to 200MHz.
- add default/sleep pinctrl.

Co-developed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Shawn Guo July 18, 2023, 3:29 a.m. UTC | #1 
On Sun, Jun 25, 2023 at 08:42:36PM +0800, Peng Fan (OSS) wrote:
> From: Han Xu <han.xu@nxp.com>
> 
> Add spi-nor support.
> - 8 bit mode for RX/TX.
> - Set the clock rate to 200MHz.
> - add default/sleep pinctrl.
> 
> Co-developed-by: Haibo Chen <haibo.chen@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> Signed-off-by: Han Xu <han.xu@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index d66e31cf83fe..e459dc35e469 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -95,6 +95,23 @@ &cm33 {
>  	status = "okay";
>  };
>  
> +&flexspi2 {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&pinctrl_flexspi2_ptd>;
> +	pinctrl-1 = <&pinctrl_flexspi2_ptd>;
> +	status = "okay";
> +
> +	mx25uw51345gxdi00: flash@0 {
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";

We usually start the property list with 'compatible'.

Shawn

> +		spi-max-frequency = <200000000>;
> +		spi-tx-bus-width = <8>;
> +		spi-rx-bus-width = <8>;


> +	};
> +};
> +
>  &lpuart5 {
>  	/* console */
>  	pinctrl-names = "default", "sleep";
> @@ -159,6 +176,23 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>  		>;
>  	};
>  
> +	pinctrl_flexspi2_ptd: flexspi2ptdgrp {
> +		fsl,pins = <
> +
> +			MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B	0x42
> +			MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK	0x42
> +			MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3	0x42
> +			MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2	0x42
> +			MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1	0x42
> +			MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0	0x42
> +			MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS	0x42
> +			MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7	0x42
> +			MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6	0x42
> +			MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5	0x42
> +			MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4	0x42
> +		>;
> +	};
> +
>  	pinctrl_lpuart5: lpuart5grp {
>  		fsl,pins = <
>  			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
> -- 
> 2.37.1
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index d66e31cf83fe..e459dc35e469 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -95,6 +95,23 @@  &cm33 {
 	status = "okay";
 };
 
+&flexspi2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_flexspi2_ptd>;
+	pinctrl-1 = <&pinctrl_flexspi2_ptd>;
+	status = "okay";
+
+	mx25uw51345gxdi00: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <200000000>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+	};
+};
+
 &lpuart5 {
 	/* console */
 	pinctrl-names = "default", "sleep";
@@ -159,6 +176,23 @@  MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
 		>;
 	};
 
+	pinctrl_flexspi2_ptd: flexspi2ptdgrp {
+		fsl,pins = <
+
+			MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B	0x42
+			MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK	0x42
+			MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3	0x42
+			MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2	0x42
+			MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1	0x42
+			MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0	0x42
+			MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS	0x42
+			MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7	0x42
+			MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6	0x42
+			MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5	0x42
+			MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4	0x42
+		>;
+	};
+
 	pinctrl_lpuart5: lpuart5grp {
 		fsl,pins = <
 			MX8ULP_PAD_PTF14__LPUART5_TX	0x3