[08/15] drm/msm/dpu: Add SM6125 support
Commit Message
Add definitions for the display hardware used on the Qualcomm SM6125
platform.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 173 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 181 insertions(+)
Comments
On 24.06.2023 02:41, Marijn Suijten wrote:
> Add definitions for the display hardware used on the Qualcomm SM6125
> platform.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
[...]
> +static const struct dpu_perf_cfg sm6125_perf_data = {
> + .max_bw_low = 4100000,
> + .max_bw_high = 4100000,
> + .min_core_ib = 2400000,
> + .min_llcc_ib = 800000,
While Dmitry will likely validate other values, I can tell you already
that this SoC has no LLCC.
Konrad
> + .min_dram_ib = 800000,
> + .min_prefill_lines = 24,
> + .danger_lut_tbl = {0xf, 0xffff, 0x0},
> + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm8150_qos_linear),
> + .entries = sm8150_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> + .entries = sc7180_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + /* TODO: macrotile-qseed is different from macrotile */
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6125_cfg = {
> + .caps = &sm6125_dpu_caps,
> + .ubwc = &sm6125_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6125_mdp),
> + .mdp = sm6125_mdp,
> + .ctl_count = ARRAY_SIZE(sm6125_ctl),
> + .ctl = sm6125_ctl,
> + .sspp_count = ARRAY_SIZE(sm6125_sspp),
> + .sspp = sm6125_sspp,
> + .mixer_count = ARRAY_SIZE(sm6125_lm),
> + .mixer = sm6125_lm,
> + .dspp_count = ARRAY_SIZE(sm6125_dspp),
> + .dspp = sm6125_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6125_pp),
> + .pingpong = sm6125_pp,
> + .intf_count = ARRAY_SIZE(sm6125_intf),
> + .intf = sm6125_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .perf = &sm6125_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF1_TEAR_INTR),
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 0de507d4d7b7..8a02bbdaae8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -33,6 +33,9 @@
> #define VIG_SC7180_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
>
> +#define VIG_SM6125_MASK \
> + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
> +
> #define VIG_SC7180_MASK_SDMA \
> (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
>
> @@ -348,6 +351,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
>
> static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
> _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
> +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
> + _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE);
>
> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
> _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
> @@ -762,6 +767,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>
> #include "catalog/dpu_5_0_sm8150.h"
> #include "catalog/dpu_5_1_sc8180x.h"
> +#include "catalog/dpu_5_4_sm6125.h"
>
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index b860784ade72..4314235cb2b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -861,6 +861,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index aa8499de1b9f..a1c7ffb6dffb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>
On 2023-06-24 03:47:27, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > Add definitions for the display hardware used on the Qualcomm SM6125
> > platform.
> >
> > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> > ---
> [...]
>
> > +static const struct dpu_perf_cfg sm6125_perf_data = {
> > + .max_bw_low = 4100000,
> > + .max_bw_high = 4100000,
> > + .min_core_ib = 2400000,
> > + .min_llcc_ib = 800000,
> While Dmitry will likely validate other values
Lovely.
> I can tell you already that this SoC has no LLCC.
Copy-paste error on downstream?
https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.9.11.c25/arch/arm64/boot/dts/qcom/trinket-sde.dtsi#L146
- Marijn
>
> Konrad
> > + .min_dram_ib = 800000,
> > + .min_prefill_lines = 24,
> > + .danger_lut_tbl = {0xf, 0xffff, 0x0},
> > + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sm8150_qos_linear),
> > + .entries = sm8150_qos_linear
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> > + .entries = sc7180_qos_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + /* TODO: macrotile-qseed is different from macrotile */
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > +const struct dpu_mdss_cfg dpu_sm6125_cfg = {
> > + .caps = &sm6125_dpu_caps,
> > + .ubwc = &sm6125_ubwc_cfg,
> > + .mdp_count = ARRAY_SIZE(sm6125_mdp),
> > + .mdp = sm6125_mdp,
> > + .ctl_count = ARRAY_SIZE(sm6125_ctl),
> > + .ctl = sm6125_ctl,
> > + .sspp_count = ARRAY_SIZE(sm6125_sspp),
> > + .sspp = sm6125_sspp,
> > + .mixer_count = ARRAY_SIZE(sm6125_lm),
> > + .mixer = sm6125_lm,
> > + .dspp_count = ARRAY_SIZE(sm6125_dspp),
> > + .dspp = sm6125_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm6125_pp),
> > + .pingpong = sm6125_pp,
> > + .intf_count = ARRAY_SIZE(sm6125_intf),
> > + .intf = sm6125_intf,
> > + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> > + .vbif = sdm845_vbif,
> > + .perf = &sm6125_perf_data,
> > + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_INTR) | \
> > + BIT(MDP_INTF1_INTR) | \
> > + BIT(MDP_INTF1_TEAR_INTR),
> > +};
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 0de507d4d7b7..8a02bbdaae8a 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -33,6 +33,9 @@
> > #define VIG_SC7180_MASK \
> > (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
> >
> > +#define VIG_SM6125_MASK \
> > + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
> > +
> > #define VIG_SC7180_MASK_SDMA \
> > (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
> >
> > @@ -348,6 +351,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
> >
> > static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
> > _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
> > +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
> > + _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE);
> >
> > static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
> > _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
> > @@ -762,6 +767,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> >
> > #include "catalog/dpu_5_0_sm8150.h"
> > #include "catalog/dpu_5_1_sc8180x.h"
> > +#include "catalog/dpu_5_4_sm6125.h"
> >
> > #include "catalog/dpu_6_0_sm8250.h"
> > #include "catalog/dpu_6_2_sc7180.h"
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index b860784ade72..4314235cb2b8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -861,6 +861,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> > extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> > extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> > extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> > +extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
> > extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> > extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> > extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index aa8499de1b9f..a1c7ffb6dffb 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
> > { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> > { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> > { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> > + { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
> > { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> > { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> > { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> >
On 25.06.2023 22:19, Marijn Suijten wrote:
> On 2023-06-24 03:47:27, Konrad Dybcio wrote:
>> On 24.06.2023 02:41, Marijn Suijten wrote:
>>> Add definitions for the display hardware used on the Qualcomm SM6125
>>> platform.
>>>
>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
>>> ---
>> [...]
>>
>>> +static const struct dpu_perf_cfg sm6125_perf_data = {
>>> + .max_bw_low = 4100000,
>>> + .max_bw_high = 4100000,
>>> + .min_core_ib = 2400000,
>>> + .min_llcc_ib = 800000,
>> While Dmitry will likely validate other values
>
> Lovely.
>
>> I can tell you already that this SoC has no LLCC.
>
> Copy-paste error on downstream?
>
> https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.9.11.c25/arch/arm64/boot/dts/qcom/trinket-sde.dtsi#L146
>
> - Marijn
Yes.
This code is bogus anyway and is just supposed to vote on DDR_FREQ_MIN
Konrad
>
>>
>> Konrad
>>> + .min_dram_ib = 800000,
>>> + .min_prefill_lines = 24,
>>> + .danger_lut_tbl = {0xf, 0xffff, 0x0},
>>> + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
>>> + .qos_lut_tbl = {
>>> + {.nentry = ARRAY_SIZE(sm8150_qos_linear),
>>> + .entries = sm8150_qos_linear
>>> + },
>>> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
>>> + .entries = sc7180_qos_macrotile
>>> + },
>>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>>> + .entries = sc7180_qos_nrt
>>> + },
>>> + /* TODO: macrotile-qseed is different from macrotile */
>>> + },
>>> + .cdp_cfg = {
>>> + {.rd_enable = 1, .wr_enable = 1},
>>> + {.rd_enable = 1, .wr_enable = 0}
>>> + },
>>> + .clk_inefficiency_factor = 105,
>>> + .bw_inefficiency_factor = 120,
>>> +};
>>> +
>>> +const struct dpu_mdss_cfg dpu_sm6125_cfg = {
>>> + .caps = &sm6125_dpu_caps,
>>> + .ubwc = &sm6125_ubwc_cfg,
>>> + .mdp_count = ARRAY_SIZE(sm6125_mdp),
>>> + .mdp = sm6125_mdp,
>>> + .ctl_count = ARRAY_SIZE(sm6125_ctl),
>>> + .ctl = sm6125_ctl,
>>> + .sspp_count = ARRAY_SIZE(sm6125_sspp),
>>> + .sspp = sm6125_sspp,
>>> + .mixer_count = ARRAY_SIZE(sm6125_lm),
>>> + .mixer = sm6125_lm,
>>> + .dspp_count = ARRAY_SIZE(sm6125_dspp),
>>> + .dspp = sm6125_dspp,
>>> + .pingpong_count = ARRAY_SIZE(sm6125_pp),
>>> + .pingpong = sm6125_pp,
>>> + .intf_count = ARRAY_SIZE(sm6125_intf),
>>> + .intf = sm6125_intf,
>>> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
>>> + .vbif = sdm845_vbif,
>>> + .perf = &sm6125_perf_data,
>>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>>> + BIT(MDP_INTF0_INTR) | \
>>> + BIT(MDP_INTF1_INTR) | \
>>> + BIT(MDP_INTF1_TEAR_INTR),
>>> +};
>>> +
>>> +#endif
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index 0de507d4d7b7..8a02bbdaae8a 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -33,6 +33,9 @@
>>> #define VIG_SC7180_MASK \
>>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
>>>
>>> +#define VIG_SM6125_MASK \
>>> + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
>>> +
>>> #define VIG_SC7180_MASK_SDMA \
>>> (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
>>>
>>> @@ -348,6 +351,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
>>>
>>> static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
>>> _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
>>> +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
>>> + _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE);
>>>
>>> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
>>> _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
>>> @@ -762,6 +767,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>>>
>>> #include "catalog/dpu_5_0_sm8150.h"
>>> #include "catalog/dpu_5_1_sc8180x.h"
>>> +#include "catalog/dpu_5_4_sm6125.h"
>>>
>>> #include "catalog/dpu_6_0_sm8250.h"
>>> #include "catalog/dpu_6_2_sc7180.h"
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> index b860784ade72..4314235cb2b8 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -861,6 +861,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index aa8499de1b9f..a1c7ffb6dffb 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
>>> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>>
new file mode 100644
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved.
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_5_4_SM6125_H
+#define _DPU_5_4_SM6125_H
+
+static const struct dpu_caps sm6125_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x6,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_10,
+ .highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x1,
+};
+
+static const struct dpu_mdp_cfg sm6125_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45c,
+ .features = 0,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6125_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6125_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SM6125_MASK,
+ sm6125_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+};
+
+static const struct dpu_lm_cfg sm6125_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_QCM2290_MASK,
+ &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6125_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6125_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6125_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24,
+ INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_perf_cfg sm6125_perf_data = {
+ .max_bw_low = 4100000,
+ .max_bw_high = 4100000,
+ .min_core_ib = 2400000,
+ .min_llcc_ib = 800000,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
+ .entries = sm8150_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6125_cfg = {
+ .caps = &sm6125_dpu_caps,
+ .ubwc = &sm6125_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6125_mdp),
+ .mdp = sm6125_mdp,
+ .ctl_count = ARRAY_SIZE(sm6125_ctl),
+ .ctl = sm6125_ctl,
+ .sspp_count = ARRAY_SIZE(sm6125_sspp),
+ .sspp = sm6125_sspp,
+ .mixer_count = ARRAY_SIZE(sm6125_lm),
+ .mixer = sm6125_lm,
+ .dspp_count = ARRAY_SIZE(sm6125_dspp),
+ .dspp = sm6125_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6125_pp),
+ .pingpong = sm6125_pp,
+ .intf_count = ARRAY_SIZE(sm6125_intf),
+ .intf = sm6125_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6125_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
@@ -33,6 +33,9 @@
#define VIG_SC7180_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+#define VIG_SM6125_MASK \
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+
#define VIG_SC7180_MASK_SDMA \
(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
@@ -348,6 +351,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
+static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
+ _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
@@ -762,6 +767,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_5_0_sm8150.h"
#include "catalog/dpu_5_1_sc8180x.h"
+#include "catalog/dpu_5_4_sm6125.h"
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
@@ -861,6 +861,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
@@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },