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[GIT,PULL] irqchip updates for 6.5

Message ID 20230623224345.3577134-1-maz@kernel.org
State New
Headers
Series [GIT,PULL] irqchip updates for 6.5 |

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-6.5

Message

Marc Zyngier June 23, 2023, 10:43 p.m. UTC 
  Thomas,

Here's the set of irqchip patches for 6.5. The only notable bit
is the workaround for the GICv3 LPIs lacking an active state
and having to be retriggered when firing concurrently on multiple
CPUs. The rest is pretty benign, with mostly a bunch of Loongson
fixes, errata workarounds, and various cleanups.

Please pull,

        M.

The following changes since commit 7877cb91f1081754a1487c144d85dc0d2e2e7fc4:

  Linux 6.4-rc4 (2023-05-28 07:49:00 -0400)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-6.5

for you to fetch changes up to a82f3119d543406ed5b242deabf83cdecb9fe523:

  Merge branch irq/misc-6.5 into irq/irqchip-next (2023-06-21 13:53:41 +0100)

----------------------------------------------------------------
irqchip updates for 6.5

- A number of Loogson/Loogarch fixes

- Allow the core code to retrigger an interrupt that has
  fired while the same interrupt is being handled on another
  CPU, papering over a GICv3 architecture issue

- Work around an integration problem on ASR8601, where the CPU
  numbering isn't representable in the GIC implementation...

- Add some missing interrupt to the STM32 irqchip

- A bunch of warning squashing triggered by W=1 builds

----------------------------------------------------------------
Antonio Borneo (1):
      irqchip/stm32-exti: Fix warning on initialized field overwritten

Arnd Bergmann (6):
      irqdomain: Include internals.h for function prototypes
      irqchip/ftintc010: Mark all function static
      irqchip/mmp: Remove non-DT codepath
      irqchip/clps711x: Remove unused clps711x_intc_init() function
      irqchip/mxs: Include linux/irqchip/mxs.h
      irqchip/gicv3: Add a iort_pmsi_get_dev_id() prototype

Binbin Zhou (2):
      dt-bindings: interrupt-controller: Add Loongson EIOINTC
      irqchip/loongson-eiointc: Add DT init support

James Gowans (3):
      genirq: Expand doc for PENDING and REPLAY flags
      genirq: Allow fasteoi handler to resend interrupts on concurrent handling
      irqchip/gic-v3-its: Enable RESEND_WHEN_IN_PROGRESS for LPIs

Jianmin Lv (3):
      irqchip/loongson-pch-pic: Fix initialization of HT vector register
      irqchip/loongson-liointc: Fix IRQ trigger polarity
      irqchip/loongson-eiointc: Fix irq affinity setting during resume

John Paul Adrian Glaubitz (1):
      irqchip/jcore-aic: Fix missing allocation of IRQ descriptors

Liu Peibao (1):
      irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment

Marc Zyngier (7):
      irqchip/gic-v3: Improve affinity helper
      Merge branch irq/gic-v3-asr8601 into irq/irqchip-next
      genirq: Use BIT() for the IRQD_* state flags
      Merge branch irq/lpi-resend into irq/irqchip-next
      Merge branch irq/loongarch-fixes-6.5 into irq/irqchip-next
      Revert "irqchip/mxs: Include linux/irqchip/mxs.h"
      Merge branch irq/misc-6.5 into irq/irqchip-next

Marek Vasut (1):
      irqchip/stm32-exti: Add STM32MP15xx IWDG2 EXTI to GIC map

Yinbo Zhu (1):
      irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag

zhengyan (1):
      irqchip/gic-v3: Work around affinity issues on ASR8601

 Documentation/arm64/silicon-errata.rst             |   4 +
 .../interrupt-controller/loongson,eiointc.yaml     |  59 +++++++++
 drivers/irqchip/irq-clps711x.c                     |   7 --
 drivers/irqchip/irq-ftintc010.c                    |   4 +-
 drivers/irqchip/irq-gic-v3-its.c                   |   2 +
 drivers/irqchip/irq-gic-v3.c                       |  45 +++++--
 drivers/irqchip/irq-jcore-aic.c                    |   7 ++
 drivers/irqchip/irq-loongson-eiointc.c             | 135 +++++++++++++++------
 drivers/irqchip/irq-loongson-liointc.c             |  13 +-
 drivers/irqchip/irq-loongson-pch-pic.c             |  10 +-
 drivers/irqchip/irq-mmp.c                          | 127 -------------------
 drivers/irqchip/irq-stm32-exti.c                   |  13 ++
 include/linux/acpi_iort.h                          |   3 +-
 include/linux/irq.h                                |  59 +++++----
 include/linux/irqchip/mmp.h                        |  10 --
 kernel/irq/chip.c                                  |  16 ++-
 kernel/irq/debugfs.c                               |   2 +
 kernel/irq/internals.h                             |   7 +-
 kernel/irq/irqdomain.c                             |   2 +
 19 files changed, 296 insertions(+), 229 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,eiointc.yaml
 delete mode 100644 include/linux/irqchip/mmp.h

Comments

tip-bot2 for Thomas Gleixner June 26, 2023, 9:10 a.m. UTC | #1 
The following commit has been merged into the irq/core branch of tip:

Commit-ID:     f121ab7f4ac32ed2aa51035534926f9507a8308b
Gitweb:        https://git.kernel.org/tip/f121ab7f4ac32ed2aa51035534926f9507a8308b
Author:        Thomas Gleixner <tglx@linutronix.de>
AuthorDate:    Mon, 26 Jun 2023 11:05:49 +02:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 26 Jun 2023 11:05:49 +02:00

Merge tag 'irqchip-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier:

  - A number of Loogson/Loogarch fixes

  - Allow the core code to retrigger an interrupt that has
    fired while the same interrupt is being handled on another
    CPU, papering over a GICv3 architecture issue

  - Work around an integration problem on ASR8601, where the CPU
    numbering isn't representable in the GIC implementation...

  - Add some missing interrupt to the STM32 irqchip

  - A bunch of warning squashing triggered by W=1 builds

Link: https://lore.kernel.org/r/20230623224345.3577134-1-maz@kernel.org
---