diff mbox series

RISC-V: Show accurate per-hart isa in /proc/cpuinfo

Message ID 20230623222353.3742384-1-evan@rivosinc.com
State New
Headers
Series RISC-V: Show accurate per-hart isa in /proc/cpuinfo |

Commit Message

Evan Green June 23, 2023, 10:23 p.m. UTC 
  In /proc/cpuinfo, most of the information we show for each processor is
specific to that hart: marchid, mvendorid, mimpid, processor, hart,
compatible, and the mmu size. But the ISA string gets filtered through a
lowest common denominator mask, so that if one CPU is missing an ISA
extension, no CPUs will show it.

Now that we track the ISA extensions for each hart, let's report ISA
extension info accurately per-hart in /proc/cpuinfo.

Signed-off-by: Evan Green <evan@rivosinc.com>

---

 arch/riscv/kernel/cpu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

Comments

Conor Dooley June 24, 2023, 12:12 a.m. UTC | #1 
Hey Evan,

On Fri, Jun 23, 2023 at 03:23:53PM -0700, Evan Green wrote:
> In /proc/cpuinfo, most of the information we show for each processor is
> specific to that hart: marchid, mvendorid, mimpid, processor, hart,
> compatible, and the mmu size. But the ISA string gets filtered through a
> lowest common denominator mask, so that if one CPU is missing an ISA
> extension, no CPUs will show it.
> 
> Now that we track the ISA extensions for each hart, let's report ISA
> extension info accurately per-hart in /proc/cpuinfo.

No, you can't do this as it breaks the assumptions of userspace that
this shows the set supported across all harts.
Sorry, but NAK.

Cheers,
Conor.
Evan Green June 26, 2023, 7:25 p.m. UTC | #2 
On Fri, Jun 23, 2023 at 5:12 PM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Evan,
>
> On Fri, Jun 23, 2023 at 03:23:53PM -0700, Evan Green wrote:
> > In /proc/cpuinfo, most of the information we show for each processor is
> > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
> > compatible, and the mmu size. But the ISA string gets filtered through a
> > lowest common denominator mask, so that if one CPU is missing an ISA
> > extension, no CPUs will show it.
> >
> > Now that we track the ISA extensions for each hart, let's report ISA
> > extension info accurately per-hart in /proc/cpuinfo.
>
> No, you can't do this as it breaks the assumptions of userspace that
> this shows the set supported across all harts.
> Sorry, but NAK.

My hope was that we were still early enough that no production systems
existed (yet) that actually had different ISA extensions in the set we
track, and therefore usermode would have been unable to make those
assumptions at this point. If such a system exists, and I don't know
if it does or not, then I agree it's too late to make a change like
this.

I thought I'd put this out here and see if someone could point at such
a system; but if not it'd be great to keep /proc/cpuinfo accurate and
consistent with hwprobe (which does return accurate per-hart ISA
extension info).

-Evan

>
> Cheers,
> Conor.
Conor Dooley June 26, 2023, 8:34 p.m. UTC | #3 
On Mon, Jun 26, 2023 at 12:25:42PM -0700, Evan Green wrote:
> On Fri, Jun 23, 2023 at 5:12 PM Conor Dooley <conor@kernel.org> wrote:
> > On Fri, Jun 23, 2023 at 03:23:53PM -0700, Evan Green wrote:
> > > In /proc/cpuinfo, most of the information we show for each processor is
> > > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
> > > compatible, and the mmu size. But the ISA string gets filtered through a
> > > lowest common denominator mask, so that if one CPU is missing an ISA
> > > extension, no CPUs will show it.
> > >
> > > Now that we track the ISA extensions for each hart, let's report ISA
> > > extension info accurately per-hart in /proc/cpuinfo.
> >
> > No, you can't do this as it breaks the assumptions of userspace that
> > this shows the set supported across all harts.
> > Sorry, but NAK.

> My hope was that we were still early enough that no production systems
> existed (yet) that actually had different ISA extensions in the set we
> track, and therefore usermode would have been unable to make those
> assumptions at this point. If such a system exists, and I don't know
> if it does or not, then I agree it's too late to make a change like
> this.

You should put this information into your commit messages & not just
hope that people understand your intent.
Userspace does actually make these assumptions already, see for example
this Google "cpu features" repo:
https://github.com/google/cpu_features/tree/main
To be quite honest, I really dislike the fragility of what they have
implemented - with only one of the reasons being they made the mistake
of assuming homogeneity.

There's got to be a line somewhere for what constitutes buggy userspace
and what's a regression. Up to Palmer I suppose as to what constitutes
which.

> I thought I'd put this out here and see if someone could point at such
> a system; but if not it'd be great to keep /proc/cpuinfo accurate and
> consistent with hwprobe (which does return accurate per-hart ISA
> extension info).

Just another nail in the coffin for a bad interface :)
There are apparently some mixed c906 chips that support vector on one
core and not the other - although it is thead vector which is not
supported upstream yet...

Other than that, SiFive stuff technically can be mixed - rv64imac &
rv64imafdc on a bunch of the older stuff. I don't think anyone actually
runs those sort of configurations on them though.
Palmer Dabbelt June 26, 2023, 8:48 p.m. UTC | #4 
On Mon, 26 Jun 2023 13:34:24 PDT (-0700), Conor Dooley wrote:
> On Mon, Jun 26, 2023 at 12:25:42PM -0700, Evan Green wrote:
>> On Fri, Jun 23, 2023 at 5:12 PM Conor Dooley <conor@kernel.org> wrote:
>> > On Fri, Jun 23, 2023 at 03:23:53PM -0700, Evan Green wrote:
>> > > In /proc/cpuinfo, most of the information we show for each processor is
>> > > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
>> > > compatible, and the mmu size. But the ISA string gets filtered through a
>> > > lowest common denominator mask, so that if one CPU is missing an ISA
>> > > extension, no CPUs will show it.
>> > >
>> > > Now that we track the ISA extensions for each hart, let's report ISA
>> > > extension info accurately per-hart in /proc/cpuinfo.
>> >
>> > No, you can't do this as it breaks the assumptions of userspace that
>> > this shows the set supported across all harts.
>> > Sorry, but NAK.
>
>> My hope was that we were still early enough that no production systems
>> existed (yet) that actually had different ISA extensions in the set we
>> track, and therefore usermode would have been unable to make those
>> assumptions at this point. If such a system exists, and I don't know
>> if it does or not, then I agree it's too late to make a change like
>> this.
>
> You should put this information into your commit messages & not just
> hope that people understand your intent.
> Userspace does actually make these assumptions already, see for example
> this Google "cpu features" repo:
> https://github.com/google/cpu_features/tree/main
> To be quite honest, I really dislike the fragility of what they have
> implemented - with only one of the reasons being they made the mistake
> of assuming homogeneity.
>
> There's got to be a line somewhere for what constitutes buggy userspace
> and what's a regression. Up to Palmer I suppose as to what constitutes
> which.

Maybe let's just add a pretty printed version of the hwprobe info to 
/proc/cpuinfo, and then leave the ISA string alone as a legacy 
interface?

Having something so poorly defined as uABI is a bit embarassing, but 
it's our mistake so we've got to live with it.

>> I thought I'd put this out here and see if someone could point at such
>> a system; but if not it'd be great to keep /proc/cpuinfo accurate and
>> consistent with hwprobe (which does return accurate per-hart ISA
>> extension info).
>
> Just another nail in the coffin for a bad interface :)
> There are apparently some mixed c906 chips that support vector on one
> core and not the other - although it is thead vector which is not
> supported upstream yet...
>
> Other than that, SiFive stuff technically can be mixed - rv64imac &
> rv64imafdc on a bunch of the older stuff. I don't think anyone actually
> runs those sort of configurations on them though.
Evan Green June 26, 2023, 11:19 p.m. UTC | #5 
On Mon, Jun 26, 2023 at 1:48 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Mon, 26 Jun 2023 13:34:24 PDT (-0700), Conor Dooley wrote:
> > On Mon, Jun 26, 2023 at 12:25:42PM -0700, Evan Green wrote:
> >> On Fri, Jun 23, 2023 at 5:12 PM Conor Dooley <conor@kernel.org> wrote:
> >> > On Fri, Jun 23, 2023 at 03:23:53PM -0700, Evan Green wrote:
> >> > > In /proc/cpuinfo, most of the information we show for each processor is
> >> > > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
> >> > > compatible, and the mmu size. But the ISA string gets filtered through a
> >> > > lowest common denominator mask, so that if one CPU is missing an ISA
> >> > > extension, no CPUs will show it.
> >> > >
> >> > > Now that we track the ISA extensions for each hart, let's report ISA
> >> > > extension info accurately per-hart in /proc/cpuinfo.
> >> >
> >> > No, you can't do this as it breaks the assumptions of userspace that
> >> > this shows the set supported across all harts.
> >> > Sorry, but NAK.
> >
> >> My hope was that we were still early enough that no production systems
> >> existed (yet) that actually had different ISA extensions in the set we
> >> track, and therefore usermode would have been unable to make those
> >> assumptions at this point. If such a system exists, and I don't know
> >> if it does or not, then I agree it's too late to make a change like
> >> this.
> >
> > You should put this information into your commit messages & not just
> > hope that people understand your intent.

Fair enough.

> > Userspace does actually make these assumptions already, see for example
> > this Google "cpu features" repo:
> > https://github.com/google/cpu_features/tree/main
> > To be quite honest, I really dislike the fragility of what they have
> > implemented - with only one of the reasons being they made the mistake
> > of assuming homogeneity.

> >
> > There's got to be a line somewhere for what constitutes buggy userspace
> > and what's a regression. Up to Palmer I suppose as to what constitutes
> > which.
>
> Maybe let's just add a pretty printed version of the hwprobe info to
> /proc/cpuinfo, and then leave the ISA string alone as a legacy
> interface?

I like it! I'll aim for that for v2. I'll resist the urge to name the
row isa_for_real.

>
> Having something so poorly defined as uABI is a bit embarassing, but
> it's our mistake so we've got to live with it.
>
> >> I thought I'd put this out here and see if someone could point at such
> >> a system; but if not it'd be great to keep /proc/cpuinfo accurate and
> >> consistent with hwprobe (which does return accurate per-hart ISA
> >> extension info).
> >
> > Just another nail in the coffin for a bad interface :)
> > There are apparently some mixed c906 chips that support vector on one
> > core and not the other - although it is thead vector which is not
> > supported upstream yet...
> >
> > Other than that, SiFive stuff technically can be mixed - rv64imac &
> > rv64imafdc on a bunch of the older stuff. I don't think anyone actually
> > runs those sort of configurations on them though.
diff mbox series

Patch

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..7bb386f94f01 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -226,7 +226,7 @@  static struct riscv_isa_ext_data isa_ext_arr[] = {
 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
 };
 
-static void print_isa_ext(struct seq_file *f)
+static void print_isa_ext(struct seq_file *f, unsigned long cpu)
 {
 	struct riscv_isa_ext_data *edata;
 	int i = 0, arr_sz;
@@ -239,7 +239,8 @@  static void print_isa_ext(struct seq_file *f)
 
 	for (i = 0; i <= arr_sz; i++) {
 		edata = &isa_ext_arr[i];
-		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+		if (!__riscv_isa_extension_available(hart_isa[cpu].isa,
+						     edata->isa_ext_id))
 			continue;
 		seq_printf(f, "_%s", edata->uprop);
 	}
@@ -253,7 +254,7 @@  static void print_isa_ext(struct seq_file *f)
  */
 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
 
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f, const char *isa, unsigned long cpu)
 {
 	int i;
 
@@ -261,11 +262,12 @@  static void print_isa(struct seq_file *f, const char *isa)
 	/* Print the rv[64/32] part */
 	seq_write(f, isa, 4);
 	for (i = 0; i < sizeof(base_riscv_exts); i++) {
-		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
+		if (__riscv_isa_extension_available(hart_isa[cpu].isa,
+						    base_riscv_exts[i] - 'a'))
 			/* Print only enabled the base ISA extensions */
 			seq_write(f, &base_riscv_exts[i], 1);
 	}
-	print_isa_ext(f);
+	print_isa_ext(f, cpu);
 	seq_puts(f, "\n");
 }
 
@@ -324,7 +326,7 @@  static int c_show(struct seq_file *m, void *v)
 	if (acpi_disabled) {
 		node = of_get_cpu_node(cpu_id, NULL);
 		if (!of_property_read_string(node, "riscv,isa", &isa))
-			print_isa(m, isa);
+			print_isa(m, isa, cpu_id);
 
 		print_mmu(m);
 		if (!of_property_read_string(node, "compatible", &compat) &&
@@ -334,7 +336,7 @@  static int c_show(struct seq_file *m, void *v)
 		of_node_put(node);
 	} else {
 		if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
-			print_isa(m, isa);
+			print_isa(m, isa, cpu_id);
 
 		print_mmu(m);
 	}