diff mbox series

[v2,1/1] net: axienet: Move reset before DMA detection

Message ID 20230622175200.74033-1-fido_max@inbox.ru
State New
Headers
Series [v2,1/1] net: axienet: Move reset before DMA detection |

Commit Message

Maxim Kochetkov June 22, 2023, 5:52 p.m. UTC 
  DMA detection will fail if axinet was started before (by boot loader,
boot ROM, etc). In this state axinet will not start properly.
XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to detect
64 DMA capability here. But datasheet says: When DMACR.RS is 1
(axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
is used to fetch the first descriptor. So iowrite32()/ioread32() trick
to this register to detect DMA will not work.
So move axinet reset before DMA detection.

Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO access")
Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Robert Hancock June 22, 2023, 6:02 p.m. UTC | #1 
On Thu, 2023-06-22 at 20:52 +0300, Maxim Kochetkov wrote:
> DMA detection will fail if axinet was started before (by boot loader,
> boot ROM, etc). In this state axinet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32()
> trick
> to this register to detect DMA will not work.
> So move axinet reset before DMA detection.
> 
> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization
> prior to MDIO access")
> Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
> 

Reviewed-by: Robert Hancock <robert.hancock@calian.com>

> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct
> platform_device *pdev)
>                 goto cleanup_clk;
>         }
> 
> +       /* Reset core now that clocks are enabled, prior to accessing
> MDIO */
> +       ret = __axienet_device_reset(lp);
> +       if (ret)
> +               goto cleanup_clk;
> +
>         /* Autodetect the need for 64-bit DMA pointers.
>          * When the IP is configured for a bus width bigger than 32
> bits,
>          * writing the MSB registers is mandatory, even if they are
> all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct
> platform_device *pdev)
>         lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
>         lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
> 
> -       /* Reset core now that clocks are enabled, prior to accessing
> MDIO */
> -       ret = __axienet_device_reset(lp);
> -       if (ret)
> -               goto cleanup_clk;
> -
>         ret = axienet_mdio_setup(lp);
>         if (ret)
>                 dev_warn(&pdev->dev,
> --
> 2.40.1
>
Pandey, Radhey Shyam June 22, 2023, 6:43 p.m. UTC | #2 
> -----Original Message-----
> From: Maxim Kochetkov <fido_max@inbox.ru>
> Sent: Thursday, June 22, 2023 11:22 PM
> To: netdev@vger.kernel.org
> Cc: Maxim Kochetkov <fido_max@inbox.ru>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; David S. Miller
> <davem@davemloft.net>; Eric Dumazet <edumazet@google.com>; Jakub
> Kicinski <kuba@kernel.org>; Paolo Abeni <pabeni@redhat.com>; Simek,
> Michal <michal.simek@amd.com>; Andrew Lunn <andrew@lunn.ch>; Robert
> Hancock <robert.hancock@calian.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [PATCH v2 1/1] net: axienet: Move reset before DMA detection
> 
> DMA detection will fail if axinet was started before (by boot loader,

:%s/axinet/axienet/g

> boot ROM, etc). In this state axinet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
> to this register to detect DMA will not work.
> So move axinet reset before DMA detection.
> 
> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO

Is this fixes tag correct ? I think the failure is introduced after 
f735c40ed93c net: axienet: Autodetect 64-bit DMA capability?

> access")
> Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device
> *pdev)
>  		goto cleanup_clk;
>  	}
> 
> +	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> +	ret = __axienet_device_reset(lp);
> +	if (ret)
> +		goto cleanup_clk;
> +
>  	/* Autodetect the need for 64-bit DMA pointers.
>  	 * When the IP is configured for a bus width bigger than 32 bits,
>  	 * writing the MSB registers is mandatory, even if they are all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device
> *pdev)
>  	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
>  	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
> 
> -	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> -	ret = __axienet_device_reset(lp);
> -	if (ret)
> -		goto cleanup_clk;
> -
>  	ret = axienet_mdio_setup(lp);
>  	if (ret)
>  		dev_warn(&pdev->dev,
> --
> 2.40.1
Maxim Kochetkov June 22, 2023, 6:48 p.m. UTC | #3 
On 22.06.2023 21:43, Pandey, Radhey Shyam wrote:

>> DMA detection will fail if axinet was started before (by boot loader,
> 
> :%s/axinet/axienet/g
Sorry about that. I will fix it in v3.

> 
>> boot ROM, etc). In this state axinet will not start properly.
>> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
>> detect
>> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
>> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
>> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
>> to this register to detect DMA will not work.
>> So move axinet reset before DMA detection.
>>
>> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO
> 
> Is this fixes tag correct ? I think the failure is introduced after
> f735c40ed93c net: axienet: Autodetect 64-bit DMA capability?

Yes of course. I will fix it in v3.
Andrew Lunn June 22, 2023, 7:18 p.m. UTC | #4 
> +	/* Reset core now that clocks are enabled, prior to accessing MDIO */
> +	ret = __axienet_device_reset(lp);
> +	if (ret)
> +		goto cleanup_clk;
> +
>  	/* Autodetect the need for 64-bit DMA pointers.

I would say the comment is now not fully correct. It probably should
be extended to include 64 bit DMA.

	Andrew
Maxim Kochetkov June 22, 2023, 7:23 p.m. UTC | #5 
On 22.06.2023 22:18, Andrew Lunn wrote:
>> +	/* Reset core now that clocks are enabled, prior to accessing MDIO */
>> +	ret = __axienet_device_reset(lp);
>> +	if (ret)
>> +		goto cleanup_clk;
>> +
>>   	/* Autodetect the need for 64-bit DMA pointers.
> 
> I would say the comment is now not fully correct. It probably should
> be extended to include 64 bit DMA.

Fixed in v4
diff mbox series

Patch

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 3e310b55bce2..734822321e0a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2042,6 +2042,11 @@  static int axienet_probe(struct platform_device *pdev)
 		goto cleanup_clk;
 	}
 
+	/* Reset core now that clocks are enabled, prior to accessing MDIO */
+	ret = __axienet_device_reset(lp);
+	if (ret)
+		goto cleanup_clk;
+
 	/* Autodetect the need for 64-bit DMA pointers.
 	 * When the IP is configured for a bus width bigger than 32 bits,
 	 * writing the MSB registers is mandatory, even if they are all 0.
@@ -2096,11 +2101,6 @@  static int axienet_probe(struct platform_device *pdev)
 	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
 	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
 
-	/* Reset core now that clocks are enabled, prior to accessing MDIO */
-	ret = __axienet_device_reset(lp);
-	if (ret)
-		goto cleanup_clk;
-
 	ret = axienet_mdio_setup(lp);
 	if (ret)
 		dev_warn(&pdev->dev,