From patchwork Thu Jun 22 14:57:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 111719 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp5133574vqr; Thu, 22 Jun 2023 08:03:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7RC+p1+bsNdX3FtTVG7m0CYsa3n3yyLVcw23RHjeFgEQtbtS7ZT1g9n2asMdOH5B7xmg/G X-Received: by 2002:a17:902:ce87:b0:1b5:6312:4c5b with SMTP id f7-20020a170902ce8700b001b563124c5bmr10904188plg.63.1687446213883; Thu, 22 Jun 2023 08:03:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687446213; cv=none; d=google.com; s=arc-20160816; b=BEhs1RlyVCM/A3I+4TZdbyctXOgd1wZB89p977yfkOG2CNB1HbVa8pPpSFdwOTe7OM PNyn5Qroow1OAHA/GmDHrAWWw5al/kjDBei7I+KBErzs68QXqeKqkM3ehY0eqctbOPz9 ormhsS0vQBKE1Ypx+Ysj78Lj0fvYV1wOY5FCQLRTf3mkaquGhHv4QkpKzTLqDdjK+MM9 cUg8kBnq7t8jB9RTtCeKxPmRXlqhIgqgD3SUxDEzZ9uB0vu6pnBT5mPaeCGj/v5Gdm8h bRhlCHoqJAW2aQRZJz1nWp1/jI++LfCu1MqvA8QkPks5k87SOj4J7r36sdRBbOKdU2O6 9FzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:subject:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:cc:to:from:dkim-signature; bh=+i6JIq0V4nwWMaJmDOwGobgHPpVBj7bJFrC5zzRbZAY=; b=KCnJTiVRuOC+OJ/pZSDbPFRkojNXZKYMqWhCVwCVSH/M7l8CP154AYyqSvY+AelY9B gNH7nWdukP8uKTbqqZkpszkf+vtOToHaNnwQQjm7J2nSF2XRPrd8cR/rhE2vGTsxLCob VKcssySe+koVev6w5QIMgbZE0vDNGqLfLFXo7z7o7tC1JTVHd4+0ujM/I7bp9b6/4V/W GId0Wx75Mi9IcWNKZ5wU3n3G9CN8m4a4N0yXZM6EKG8sj3HlKgzijeB2JPxCvWaxCSZE r1MIqSiopZ6WBHDB7vqfdfvXAZWUcEHs1frLO9nq9XRhyBJi2lgM/zsHNou3mJi8C6F2 auKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@hugovil.com header.s=x header.b=0BXQDtEM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h2-20020a170902b94200b001b025aba9f2si6461708pls.22.2023.06.22.08.03.19; Thu, 22 Jun 2023 08:03:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@hugovil.com header.s=x header.b=0BXQDtEM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232144AbjFVO7I (ORCPT + 99 others); Thu, 22 Jun 2023 10:59:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232131AbjFVO63 (ORCPT ); Thu, 22 Jun 2023 10:58:29 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0D9F1FE1; Thu, 22 Jun 2023 07:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=+i6JIq0V4nwWMaJmDOwGobgHPpVBj7bJFrC5zzRbZAY=; b=0BXQDtEMunHIKGGWzQCsR0R0Uy ktu3uugAKDFMzKqdp6StUy/Lwa6vqx7IcWh9rCG25dRItJMUMge5I8QfA0FSoe/fzSsELi3ApABXb Pz8/NL1M6xOFqEGRqiSgl1jzeWKcDMlFg+WfEr9SeM5TLfzlG6C4b+tGsjG5FBLjnTT8=; Received: from modemcable061.19-161-184.mc.videotron.ca ([184.161.19.61]:55382 helo=localhost.localdomain) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1qCLlM-0002fr-L5; Thu, 22 Jun 2023 10:58:21 -0400 From: Hugo Villeneuve To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, Hugo Villeneuve Date: Thu, 22 Jun 2023 10:57:56 -0400 Message-Id: <20230622145800.2442116-14-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230622145800.2442116-1-hugo@hugovil.com> References: <20230622145800.2442116-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 184.161.19.61 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 Subject: [PATCH v4 13/17] rtc: pcf2127: adapt time/date registers write sequence for PCF2131 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769415601362955927?= X-GMAIL-MSGID: =?utf-8?q?1769415601362955927?= From: Hugo Villeneuve The sequence for updating the time/date registers is slightly different between PCF2127/29 and PCF2131. For PCF2127/29, during write operations, the time counting circuits (memory locations 03h through 09h) are automatically blocked. For PCF2131, time/date registers write access requires setting the STOP bit and sending the clear prescaler instruction (CPR). STOP then needs to be released once write operation is completed. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 2eef65232417..3b8718aaadd7 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -33,6 +33,7 @@ #define PCF2127_REG_CTRL1 0x00 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) #define PCF2127_BIT_CTRL1_TSF1 BIT(4) +#define PCF2127_BIT_CTRL1_STOP BIT(5) /* Control register 2 */ #define PCF2127_REG_CTRL2 0x01 #define PCF2127_BIT_CTRL2_AIE BIT(1) @@ -280,13 +281,45 @@ static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) /* year */ buf[i++] = bin2bcd(tm->tm_year - 100); - /* write register's data */ + /* Write access to time registers: + * PCF2127/29: no special action required. + * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to + * be cleared after time registers are updated. + */ + if (pcf2127->cfg->type == PCF2131) { + err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, + PCF2127_BIT_CTRL1_STOP, + PCF2127_BIT_CTRL1_STOP); + if (err) { + dev_dbg(dev, "setting STOP bit failed\n"); + return err; + } + + err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET, + PCF2131_SR_RESET_CPR_CMD); + if (err) { + dev_dbg(dev, "sending CPR cmd failed\n"); + return err; + } + } + + /* write time register's data */ err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); if (err) { dev_dbg(dev, "%s: err=%d", __func__, err); return err; } + if (pcf2127->cfg->type == PCF2131) { + /* Clear STOP bit (PCF2131 only) after write is completed. */ + err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, + PCF2127_BIT_CTRL1_STOP, 0); + if (err) { + dev_dbg(dev, "clearing STOP bit failed\n"); + return err; + } + } + return 0; }