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From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
To: agross@kernel.org
Cc: andersson@kernel.org, luca@z3ntu.xyz, konrad.dybcio@linaro.org,
dmitry.baryshkov@linaro.org, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
robdclark@gmail.com, linux-arm-msm@vger.kernel.org,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>, kernel@collabora.com
Subject: [PATCH v5 3/6] iommu/qcom: Disable and reset context bank before
programming
Date: Thu, 22 Jun 2023 11:27:39 +0200
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|
| Series |
Add support for Qualcomm's legacy IOMMU v2
|
|
Commit Message
AngeloGioacchino Del Regno
June 22, 2023, 9:27 a.m. UTC
Writing the new TTBRs, TCRs and MAIRs on a previously enabled
context bank may trigger a context fault, resulting in firmware
driven AP resets: change the domain initialization programming
sequence to disable the context bank(s) and to also clear the
related fault address (CB_FAR) and fault status (CB_FSR)
registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1.
Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++
1 file changed, 7 insertions(+)
Comments
On 22.06.2023 11:27, AngeloGioacchino Del Regno wrote: > Writing the new TTBRs, TCRs and MAIRs on a previously enabled > context bank may trigger a context fault, resulting in firmware > driven AP resets: change the domain initialization programming > sequence to disable the context bank(s) and to also clear the > related fault address (CB_FAR) and fault status (CB_FSR) > registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1. > > Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > index 8face57c4180..f1bd7c035db8 100644 > --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c > +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, > ctx->secure_init = true; > } > > + /* Disable context bank before programming */ > + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); > + > + /* Clear context bank fault address fault status registers */ > + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); > + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); > + > /* TTBRs */ > iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 8face57c4180..f1bd7c035db8 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + /* Disable context bank before programming */ + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + + /* Clear context bank fault address fault status registers */ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); + /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, pgtbl_cfg.arm_lpae_s1_cfg.ttbr |