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Wed, 21 Jun 2023 18:55:46 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 05/21] iommu/amd: Refactor set_dte_entry() helper function Date: Wed, 21 Jun 2023 18:54:52 -0500 Message-ID: <20230621235508.113949-6-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|IA0PR12MB7625:EE_ X-MS-Office365-Filtering-Correlation-Id: dd94c437-1e02-4831-622e-08db72b3090d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GHCHekY8JjVpha0ypVrIWbrwQ0gPLCWww0oL2WuoWGHlR8hVjblKKbySoMGiHzhT1aGfDh4oizSa3Qt6qdR5M3rje0q/7MLmKTQrVimjVdpFP1wlb6uxaCdFblMe4M95aucRvhvTErYZLOdpGXoGvRWHFaZtH5aJNbszWaSPqv3chyEkdhe1+eRcG1/sDhM00KNkY+6QnSdhUf5a/iHWkGKthioh1eUWngv9RVvqS3Yx48XN/0e9ejDgWM3RC0i22He2TuvOoNfZ5N1M50Fdfb76mnyWDFBGluZIoOoMClCPNxr1clqdihkBb3vseYUmwd2nxPXUa+ZJQ9knatwtRxOxPkVskDOAHegxpdo5dDfxJp1YvRnz3WtrOZll4zJUsnUO2ZQCFtoMLR4rnp7EUj0t3tLoEqjS5CRbiBFw30xM1VTDrbd2LYPk+O1zJhBaiME+rgdArxy/RrhgShoZUGHGhrZNr3vj8ZCltO8/+rpt/oRiWCFF/C++yySLerbD76KarIGDnVaipEvS1DrhpmmLrhQgNEV2wiXBeosf1PZwC4ikxE5gD8zl6kkTIH+I5l5Mu5zw1/aw2odonJOiHQJvaCwGBFcguzBv8hme+XXDXSARJHIxNXs/ggzb+wnp1I3HqU2f2iLpWKY4qei31GX1UXpcmbXwgp4+pAa3DteTV9HdyiNRygXkGL2mkyeH4+BRQ5v884+OZwDEBXdt0JuplItAC8SCX9wiXyrK5Y5cxbw85nkm2PBGA+HCrWCcHu2Cm6nTDolIrjhH+1zC1w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(356005)(81166007)(36756003)(82740400003)(40480700001)(86362001)(40460700003)(82310400005)(70586007)(2616005)(41300700001)(8936002)(316002)(8676002)(478600001)(4326008)(70206006)(44832011)(47076005)(426003)(83380400001)(1076003)(336012)(7416002)(5660300002)(6666004)(7696005)(16526019)(186003)(54906003)(110136005)(26005)(36860700001)(2906002)(36900700001);DIR:OUT;SFP:1101; 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There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 72 ++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 6017fce8d7fd..3b31ecde0122 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1553,6 +1553,42 @@ static void free_gcr3_table(struct protection_domain *domain) free_page((unsigned long)domain->gcr3_tbl); } +static void set_dte_entry_v2(struct amd_iommu *iommu, + struct protection_domain *domain, + u64 *gcr3_tbl, u64 *pte_root, u64 *flags) +{ + u64 gcr3 = iommu_virt_to_phys(gcr3_tbl); + u64 glx = domain->glx; + u64 tmp; + + if (!(domain->flags & PD_IOMMUV2_MASK)) + return; + + if ((domain->flags & PD_GIOV_MASK) && + iommu_feature(iommu, FEATURE_GIOSUP)) + *pte_root |= DTE_FLAG_GIOV; + + *pte_root |= DTE_FLAG_GV; + *pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; + + /* First mask out possible old values for GCR3 table */ + tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; + *flags &= ~tmp; + + tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; + *flags &= ~tmp; + + /* Encode GCR3 table into DTE */ + tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; + *pte_root |= tmp; + + tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; + *flags |= tmp; + + tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; + *flags |= tmp; +} + void set_dte_entry(struct amd_iommu *iommu, u16 devid, struct protection_domain *domain, bool ats, bool ppr) { @@ -1586,38 +1622,12 @@ void set_dte_entry(struct amd_iommu *iommu, u16 devid, pte_root |= 1ULL << DEV_ENTRY_PPR; } - if (domain->flags & PD_IOMMUV2_MASK) { - u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); - u64 glx = domain->glx; - u64 tmp; - - pte_root |= DTE_FLAG_GV; - pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; - - /* First mask out possible old values for GCR3 table */ - tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; - flags &= ~tmp; - - tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; - flags &= ~tmp; - - /* Encode GCR3 table into DTE */ - tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; - pte_root |= tmp; - - tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; - flags |= tmp; - - tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; - flags |= tmp; - - if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) { - dev_table[devid].data[2] |= - ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); - } + set_dte_entry_v2(iommu, domain, domain->gcr3_tbl, &pte_root, &flags); - if (domain->flags & PD_GIOV_MASK) - pte_root |= DTE_FLAG_GIOV; + if ((domain->flags & PD_IOMMUV2_MASK) && + amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) { + dev_table[devid].data[2] |= + ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); } flags &= ~DEV_DOMID_MASK;