diff mbox series

[RFC,05/21] iommu/amd: Refactor set_dte_entry() helper function

Message ID 20230621235508.113949-6-suravee.suthikulpanit@amd.com
State New
Headers
Series iommu/amd: Introduce support for HW accelerated vIOMMU w/ nested page table |

Commit Message

Suravee Suthikulpanit June 21, 2023, 11:54 p.m. UTC 
  To separate logic for IOMMU guest (v2) page table into another helper
function in preparation for subsequent changes.

There is no functional change.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 drivers/iommu/amd/iommu.c | 72 ++++++++++++++++++++++-----------------
 1 file changed, 41 insertions(+), 31 deletions(-)
diff mbox series

Patch

diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 6017fce8d7fd..3b31ecde0122 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1553,6 +1553,42 @@  static void free_gcr3_table(struct protection_domain *domain)
 	free_page((unsigned long)domain->gcr3_tbl);
 }
 
+static void set_dte_entry_v2(struct amd_iommu *iommu,
+			     struct protection_domain *domain,
+			     u64 *gcr3_tbl, u64 *pte_root, u64 *flags)
+{
+	u64 gcr3 = iommu_virt_to_phys(gcr3_tbl);
+	u64 glx  = domain->glx;
+	u64 tmp;
+
+	if (!(domain->flags & PD_IOMMUV2_MASK))
+		return;
+
+	if ((domain->flags & PD_GIOV_MASK) &&
+	    iommu_feature(iommu, FEATURE_GIOSUP))
+		*pte_root |= DTE_FLAG_GIOV;
+
+	*pte_root |= DTE_FLAG_GV;
+	*pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
+
+	/* First mask out possible old values for GCR3 table */
+	tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
+	*flags    &= ~tmp;
+
+	tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
+	*flags    &= ~tmp;
+
+	/* Encode GCR3 table into DTE */
+	tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
+	*pte_root |= tmp;
+
+	tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
+	*flags    |= tmp;
+
+	tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
+	*flags    |= tmp;
+}
+
 void set_dte_entry(struct amd_iommu *iommu, u16 devid,
 		   struct protection_domain *domain, bool ats, bool ppr)
 {
@@ -1586,38 +1622,12 @@  void set_dte_entry(struct amd_iommu *iommu, u16 devid,
 			pte_root |= 1ULL << DEV_ENTRY_PPR;
 	}
 
-	if (domain->flags & PD_IOMMUV2_MASK) {
-		u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
-		u64 glx  = domain->glx;
-		u64 tmp;
-
-		pte_root |= DTE_FLAG_GV;
-		pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
-
-		/* First mask out possible old values for GCR3 table */
-		tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
-		flags    &= ~tmp;
-
-		tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
-		flags    &= ~tmp;
-
-		/* Encode GCR3 table into DTE */
-		tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
-		pte_root |= tmp;
-
-		tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
-		flags    |= tmp;
-
-		tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
-		flags    |= tmp;
-
-		if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) {
-			dev_table[devid].data[2] |=
-				((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT);
-		}
+	set_dte_entry_v2(iommu, domain, domain->gcr3_tbl, &pte_root, &flags);
 
-		if (domain->flags & PD_GIOV_MASK)
-			pte_root |= DTE_FLAG_GIOV;
+	if ((domain->flags & PD_IOMMUV2_MASK) &&
+	    amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) {
+		dev_table[devid].data[2] |=
+			((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT);
 	}
 
 	flags &= ~DEV_DOMID_MASK;