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Wed, 21 Jun 2023 18:55:53 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 12/21] iommu/amd: Introduce AMD vIOMMU-specific UAPI Date: Wed, 21 Jun 2023 18:54:59 -0500 Message-ID: <20230621235508.113949-13-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|SA0PR12MB4560:EE_ X-MS-Office365-Filtering-Correlation-Id: 65208709-462b-44ff-9034-08db72b30dc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ky6UDFtn0ptih9xO7AaC5pH083ReWvflDIojiTAbYoWtzrFM5V45f/DwauxL2imB+Loy5Qdf3JWo3MqWgajdX65kSLpeP7k20cWfTZXxxQsjcproKInUTerGNZl/UQemiuPP0qI3t21AkV8ZP5JRqjeCnaOEi2HWV2Qq+2guaqYsGyYajTWXCI8eZd/yHIUtZeQ8cv35b6j8d3qtKP29/PD3KWWIZPRmKv6bJDKwpjxPKvRR1FXwAGPxlDam+E4cnOs35fcYoDQVyWSLA6/rAfbcZk9eZsMfMH9MYyWeEatiy5t/6i3rZu6o5GVP0NmqXOtqmOgCzP6Ij5CzkxQmKBouOuq2ekwyP2WQeNbUDzqflds3vFexyn95B1bBdXnWPmJ2/Gj5VQqnB6c8YazsFwJa5l2CnPiRl7g+LQ/SGfer73ZGBtaAvU/YosWUpPtUjhkm9qRMnOojVbGJ/cTe+pT3OlpGc+koN1pRIysH0d74xuxfBbftU8Z6THGn378TefzIiaOHxNQ0pZeINkhk35rh76NUOy/Ye5gBxZQzwkDlzic2WyJF7vZPbJpwRLgq6ohKadoJe3kJ+Zkws/KyXRdQAwdy/Cwm+yn5LtbKq/7TG0J8nsprwykyU0AgMwrnJrku3ELtHPvsp2Jg64yLLmfvdg/ryorQM8WWYmHPrQIE+6quats8juhJ9khk/3eoU7aBER9ERDK5MrZm9XiRl60hfGps9Rtn+dpnGPLMRDzqooCd6s2hpeC5jSwz7H3HdFNvQ0Y9kGPV6nhpcxA7MtZ8kSd41R6pnWlunYz90E+ivpi9Fc/WJbVOMixIr5Bu X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199021)(36840700001)(40470700004)(46966006)(54906003)(110136005)(478600001)(4326008)(26005)(16526019)(186003)(1076003)(70586007)(2906002)(82310400005)(7696005)(41300700001)(7416002)(8936002)(70206006)(8676002)(44832011)(5660300002)(316002)(82740400003)(356005)(81166007)(2616005)(86362001)(36756003)(40480700001)(47076005)(426003)(336012)(83380400001)(36860700001)(40460700003)(71600200004)(36900700001);DIR:OUT;SFP:1101; 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These operations are specific to AMD hardware. Signed-off-by: Suravee Suthikulpanit --- include/uapi/linux/amd_viommu.h | 145 ++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 include/uapi/linux/amd_viommu.h diff --git a/include/uapi/linux/amd_viommu.h b/include/uapi/linux/amd_viommu.h new file mode 100644 index 000000000000..f4a91ecd5dc2 --- /dev/null +++ b/include/uapi/linux/amd_viommu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * AMD Hardwaer Accelerated Virtualized IOMMU (HW-vIOMMU) + * + * Copyright (c) 2023, Advanced Micro Devices, Inc. + * + */ +#ifndef _UAPI_AMD_VIOMMU_H_ +#define _UAPI_AMD_VIOMMU_H_ + +#include +#include + +/** + * The ioctl interfaces in this file are specific for AMD HW-vIOMMU. + * They are an extension of extend the IOMMUFD ioctl interfaces. + * Please see include/uapi/linux/iommufd.h for more detail. + */ +#include + +enum iommufd_viommu_cmd { + IOMMUFD_VIOMMU_CMD_BASE = 0x60, + IOMMUFD_CMD_IOMMU_INIT = IOMMUFD_VIOMMU_CMD_BASE, + IOMMUFD_CMD_IOMMU_DESTROY, + IOMMUFD_CMD_DEVICE_ATTACH, + IOMMUFD_CMD_DEVICE_DETACH, + IOMMUFD_CMD_DOMAIN_ATTACH, + IOMMUFD_CMD_DOMAIN_DETACH, + IOMMUFD_CMD_MMIO_ACCESS, + IOMMUFD_CMD_CMDBUF_UPDATE, +}; + +/** + * struct amd_viommu_iommu_info - ioctl(VIOMMU_IOMMU_[INIT|DESTROY]) + * @size: sizeof(struct amd_viommu_iommu_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * + * Initialize and destroy AMD HW-vIOMMU instances for the specified + * guest ID. + */ +struct amd_viommu_iommu_info { + __u32 size; + __u32 iommu_id; + __u32 gid; +}; +#define VIOMMU_IOMMU_INIT _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOMMU_INIT) +#define VIOMMU_IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOMMU_DESTROY) + +/** + * struct amd_viommu_dev_info - ioctl(VIOMMU_DEVICE_[ATTACH|DETACH]) + * @size: sizeof(struct amd_viommu_dev_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @hdev_id: host PCI device ID + * @gdev_id: guest PCI device ID + * @queue_id: guest PCI device queue ID + * + * Attach / Detach PCI device to a HW-vIOMMU instance, and program + * the IOMMU Device ID mapping table for the specified guest. + */ +struct amd_viommu_dev_info { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u16 hdev_id; + __u16 gdev_id; + __u16 queue_id; +}; + +#define VIOMMU_DEVICE_ATTACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DEVICE_ATTACH) +#define VIOMMU_DEVICE_DETACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DEVICE_DETACH) + +/** + * struct amd_viommu_dom_info - ioctl(VIOMMU_DOMAIN_[ATTACH|DETACH]) + * @size: sizeof(struct amd_viommu_dom_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @hdev_id: host PCI device ID + * @gdev_id: guest PCI device ID + * @gdom_id: guest domain ID + * + * Attach / Detach domain of a PCI device to a HW-vIOMMU instance, and program + * the IOMMU Domain ID mapping table for the specified guest. + */ +struct amd_viommu_dom_info { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u16 gdev_id; + __u16 gdom_id; +}; + +#define VIOMMU_DOMAIN_ATTACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DOMAIN_ATTACH) +#define VIOMMU_DOMAIN_DETACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DOMAIN_DETACH) + +/** + * struct amd_viommu_mmio_data- ioctl(VIOMMU_MMIO_ACCESS) + * @size: sizeof(struct amd_viommu_mmio_data) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @offset: specify MMIO offset + * @value: specify MMIO write value or retrieving MMIO read value + * @mmio_size: specify MMIO size + * @is_write: specify MMIO read (0) / write (1) + * + * - Trap guest IOMMU MMIO write to program HW-vIOMMU for the specified + * guest. + * - Trap guest IOMMU MMIO read to emulate return value for the specified + * guest. + */ +struct amd_viommu_mmio_data { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u32 offset; + __u64 value; + __u32 mmio_size; + __u8 is_write; +}; + +#define VIOMMU_MMIO_ACCESS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_MMIO_ACCESS) + +/** + * struct amd_viommu_cmdbuf_data - ioctl(VIOMMU_CMDBUF_UPDATE) + * @size: sizeof(struct amd_viommu_cmdbuf_data) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @gcmdbuf_size: guest command buffer size + * @hva: host virtual address for the guest command buffer + * + * Trap guest command buffer initialization to setup HW-vIOMMU command buffer + * for the specified guest. + */ +struct amd_viommu_cmdbuf_data { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u32 cmdbuf_size; + __u64 hva; +}; + +#define VIOMMU_CMDBUF_UPDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_CMDBUF_UPDATE) + +#endif