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Wed, 21 Jun 2023 00:48:41 -0500 From: Evan Quan To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Evan Quan Subject: [PATCH V4 6/8] drm/amd/pm: add flood detection for wbrf events Date: Wed, 21 Jun 2023 13:46:01 +0800 Message-ID: <20230621054603.1262299-7-evan.quan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621054603.1262299-1-evan.quan@amd.com> References: <20230621054603.1262299-1-evan.quan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EB:EE_|IA1PR12MB6436:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c3789f2-9ff4-4124-0e7c-08db721b4af1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zUzpRWQEWYmWrPk9zlElZDn7RQpXsmYO97SCxgsFJEkW7vj4/18JGdWGvVKP32qmY4ZSHIrJ4BhsPLTD5M8UbHkiuH577YzqsM0xTvO0TcfDA9fQr82FO5hJ9CR3/nGFuLwW0SZCYRmraNQhw7zjhfJXj1HLk8LGBbkUoi6dH6skVJaSOt2ogVDufAjHlkePb002RpZ8YNZ4AFdlGjh7XsdAw4Zj3lTaKEeu7wGdJ0GwYigJhGa8g6AZSoojBtlQo7QQhNoqOnej1SnnINKfGw+EnWVl8cBTlIFmRM7cRJ9sHzYbPT6GqngnDY+Nt+Ni1IL/kl2o8T7PW6TmZFL6tio0dUwN7aVl6gIAl6m0zINaQRbpx63v24TC+N3UYkT4wMX2faGGciFRQ52YN9sqIfAdaxaQdgd+Iz2Xg8qeJ5vGQhxQNrGdscG2wwryvH8sxqycJX86NNq8J1zruXTmv8uu/nnyBKy3zcI8V61/M531WQYOQnCkUOZ0XBNubLBO9rsT3m1bEWpanfgHBvrmoS08rLDW9YAAMZ8vegz+GAJ+kX6y1o7RnEFthhUmi7lUY7tKKXjrQy4MUgRja0v+QTjdkPkrRoQTmz33fXcE9koi84xRsccSmSLLzmg03Nu7UoBw7gGyYQvDRi1OWi4kKXhdlBr6kAiKbcRBpHA9F2eO2/wRfoLMZYIIYPp/C0Oc8V6aWGPA2HVZHT/EtT3vsGYSPtJkV5yoNfT+gntXJIMpel4NZ72uS1ozwFHJ/q18y02dgVRLZxzquAbWq96eUEw+hXrLo+Hb0O/Gyx9lKtTNLSXXWYHeeB2Etno4ftkEAeqzVcb3LbxbmDyY+Ho5LQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199021)(36840700001)(46966006)(40470700004)(82740400003)(40480700001)(8936002)(40460700003)(41300700001)(8676002)(82310400005)(921005)(2616005)(6666004)(356005)(426003)(336012)(83380400001)(81166007)(186003)(16526019)(26005)(478600001)(7696005)(47076005)(54906003)(86362001)(110136005)(316002)(36756003)(4326008)(70206006)(1076003)(44832011)(70586007)(36860700001)(5660300002)(7416002)(2906002)(36900700001)(83996005)(2101003);DIR:OUT;SFP:1101; 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Signed-off-by: Evan Quan Reviewed-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 28 ++++++++++++++++--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +++++ 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index a8efdce4607c..75d6e654b2a6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1272,6 +1272,22 @@ static void smu_wbrf_event_handler(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; + schedule_delayed_work(&smu->wbrf_delayed_work, + msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); +} + +/** + * smu_wbrf_delayed_work_handler - callback on delayed work timer expired + * + * @work: struct work_struct pointer + * + * Flood is over and driver will consume the latest exclusion ranges. + */ +static void smu_wbrf_delayed_work_handler(struct work_struct *work) +{ + struct smu_context *smu = + container_of(work, struct smu_context, wbrf_delayed_work.work); + smu_wbrf_handle_exclusion_ranges(smu); } @@ -1311,6 +1327,9 @@ static int smu_wbrf_init(struct smu_context *smu) if (!smu->wbrf_supported) return 0; + INIT_DELAYED_WORK(&smu->wbrf_delayed_work, + smu_wbrf_delayed_work_handler); + ret = amdgpu_acpi_register_wbrf_notify_handler(adev, smu_wbrf_event_handler); if (ret) @@ -1321,11 +1340,10 @@ static int smu_wbrf_init(struct smu_context *smu) * before our driver loaded. To make sure our driver * is awared of those exclusion ranges. */ - ret = smu_wbrf_handle_exclusion_ranges(smu); - if (ret) - dev_err(adev->dev, "Failed to handle wbrf exclusion ranges\n"); + schedule_delayed_work(&smu->wbrf_delayed_work, + msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); - return ret; + return 0; } /** @@ -1343,6 +1361,8 @@ static void smu_wbrf_fini(struct smu_context *smu) return; amdgpu_acpi_unregister_wbrf_notify_handler(adev); + + cancel_delayed_work_sync(&smu->wbrf_delayed_work); } static int smu_smc_hw_setup(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index ff0af3da0be2..aa63cc43d41c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -478,6 +478,12 @@ struct stb_context { #define WORKLOAD_POLICY_MAX 7 +/* + * Configure wbrf event handling pace as there can be only one + * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. + */ +#define SMU_WBRF_EVENT_HANDLING_PACE 10 + struct smu_context { struct amdgpu_device *adev; @@ -576,6 +582,7 @@ struct smu_context /* data structures for wbrf feature support */ bool wbrf_supported; + struct delayed_work wbrf_delayed_work; }; struct i2c_adapter;