From patchwork Mon Jun 19 12:41:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sui Jingfeng <15330273260@189.cn> X-Patchwork-Id: 109985 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2985093vqr; Mon, 19 Jun 2023 05:52:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7PMn2QTWHf8ietdBVYJIPLHr3xqHCA6f7DsSCwNjngF/wgvOj94yl2kg4yd6hDyuuUU4Rm X-Received: by 2002:a17:902:9b94:b0:1b0:2bc1:94bc with SMTP id y20-20020a1709029b9400b001b02bc194bcmr7087794plp.65.1687179149556; Mon, 19 Jun 2023 05:52:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687179149; cv=none; d=google.com; s=arc-20160816; b=BmrU/OURdlwvZN3yMLx3yyPA9I0jQ+V9pl1GuMsuDKfQL4FZRChKK65SPnEpibviOC 5L+Yt0/80LDKgJuz0+Wa+jmS+QBnZduItcx5F/RA7ejQmkzSvQLus77GH0m+TV19uWDb uNhbOyZlSVltgszuyklf314/HxTAWEi5bIrgjL3CID5RhXyWDbsYs7eKiRPDCwxnlEi/ dvleSQpOGhuAF241JX/vnmJuS9R9X2VmrV+Zsnw79YuLRayzskoiMeks9xEgNUmLs+HL fFTZigcTS/YnoLf5qpgkR+LCtUV9/0nhTcj/4lESw9buVWTcXwsJ5+mXyQ8m4LXgnFNO tl9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:sender :hmm_source_type:hmm_attache_num:hmm_source_ip; bh=U0SWL/JdjvOqGx7gC3JlFOSCNm1yICr30bcx3Pn/rOc=; b=CADXZVQaGBSiFb0yj6yrmHNxE7Ce2MnZmoT/4J3a+yxXjYWvMp/57wXMUEuUJnNhsW RH+GHQ2o0IZLm8PUyRwfPbWhuyIfp0k8JeTgREoLYY9ImPKlLIlPIAtweF0dF+3Mpne+ G32/kn+GOSSaxAu7N09D915kb4llqFr2HdhjoBjIdwjmRPQW9FzsLFyfWuhq6xA+HQJ7 kVaMEHlsaUqY6SqZ3L2NvsJ8ird95JhHZBTXp9qEq7F9lP90hc9Q9B4wZAdV6x4/Zm3P u9NRJ/7DUDQVyuU8M1LqJ4S0c6cgRExPOaWT34bvvGEpYYDLJwXVK1D5jGnCgHoRElwu MgNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q4-20020a170902dac400b001b672af6244si489102plx.266.2023.06.19.05.52.13; Mon, 19 Jun 2023 05:52:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230419AbjFSMmU (ORCPT + 99 others); Mon, 19 Jun 2023 08:42:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbjFSMmM (ORCPT ); Mon, 19 Jun 2023 08:42:12 -0400 Received: from 189.cn (ptr.189.cn [183.61.185.104]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E2637D7 for ; Mon, 19 Jun 2023 05:42:10 -0700 (PDT) HMM_SOURCE_IP: 10.64.8.41:49634.708654646 HMM_ATTACHE_NUM: 0000 HMM_SOURCE_TYPE: SMTP Received: from clientip-114.242.206.180 (unknown [10.64.8.41]) by 189.cn (HERMES) with SMTP id 370FF100294; Mon, 19 Jun 2023 20:42:08 +0800 (CST) Received: from ([114.242.206.180]) by gateway-151646-dep-75648544bd-xwndj with ESMTP id 335925be468247e09fde82d183bdd0ac for l.stach@pengutronix.de; Mon, 19 Jun 2023 20:42:10 CST X-Transaction-ID: 335925be468247e09fde82d183bdd0ac X-Real-From: 15330273260@189.cn X-Receive-IP: 114.242.206.180 X-MEDUSA-Status: 0 Sender: 15330273260@189.cn From: Sui Jingfeng <15330273260@189.cn> To: Lucas Stach , Russell King , Christian Gmeiner , David Airlie , Daniel Vetter Cc: linux-kernel@vger.kernel.org, etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Sui Jingfeng , Philipp Zabel , Bjorn Helgaas Subject: [PATCH v10 02/11] drm/etnaviv: Add a dedicated function to get various clocks Date: Mon, 19 Jun 2023 20:41:52 +0800 Message-Id: <20230619124201.2215558-3-15330273260@189.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619124201.2215558-1-15330273260@189.cn> References: <20230619124201.2215558-1-15330273260@189.cn> MIME-Version: 1.0 X-Spam-Status: No, score=1.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,FROM_LOCAL_DIGITS, FROM_LOCAL_HEX,RCVD_IN_SBL_CSS,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769135564087732306?= X-GMAIL-MSGID: =?utf-8?q?1769135564087732306?= From: Sui Jingfeng Because it is also platform-dependent, there are systems where we don't have DT-based clock drivers supported. For example, discrete PCI GPUs. Therefire, don't quit if there is no clock subsystem support.      For the GPU in LS7A1000 and LS2K1000, the working frequency of the GPU is rely on the GFX PLL to generate the clock. Typically, the GFX PLL is configured by the platform firmware. Cc: Lucas Stach Cc: Christian Gmeiner Cc: Philipp Zabel Cc: Bjorn Helgaas Cc: Daniel Vetter Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ++++++++++++++++----------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index a03e81337d8f..5e88fa95dac2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1565,6 +1565,35 @@ static irqreturn_t irq_handler(int irq, void *data) return ret; } +static int etnaviv_gpu_clk_get(struct etnaviv_gpu *gpu) +{ + struct device *dev = gpu->dev; + + gpu->clk_reg = devm_clk_get_optional(dev, "reg"); + DBG("clk_reg: %p", gpu->clk_reg); + if (IS_ERR(gpu->clk_reg)) + return PTR_ERR(gpu->clk_reg); + + gpu->clk_bus = devm_clk_get_optional(dev, "bus"); + DBG("clk_bus: %p", gpu->clk_bus); + if (IS_ERR(gpu->clk_bus)) + return PTR_ERR(gpu->clk_bus); + + gpu->clk_core = devm_clk_get(dev, "core"); + DBG("clk_core: %p", gpu->clk_core); + if (IS_ERR(gpu->clk_core)) + return PTR_ERR(gpu->clk_core); + gpu->base_rate_core = clk_get_rate(gpu->clk_core); + + gpu->clk_shader = devm_clk_get_optional(dev, "shader"); + DBG("clk_shader: %p", gpu->clk_shader); + if (IS_ERR(gpu->clk_shader)) + return PTR_ERR(gpu->clk_shader); + gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + + return 0; +} + static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) { int ret; @@ -1863,27 +1892,9 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) return err; /* Get Clocks: */ - gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); - DBG("clk_reg: %p", gpu->clk_reg); - if (IS_ERR(gpu->clk_reg)) - return PTR_ERR(gpu->clk_reg); - - gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); - DBG("clk_bus: %p", gpu->clk_bus); - if (IS_ERR(gpu->clk_bus)) - return PTR_ERR(gpu->clk_bus); - - gpu->clk_core = devm_clk_get(&pdev->dev, "core"); - DBG("clk_core: %p", gpu->clk_core); - if (IS_ERR(gpu->clk_core)) - return PTR_ERR(gpu->clk_core); - gpu->base_rate_core = clk_get_rate(gpu->clk_core); - - gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); - DBG("clk_shader: %p", gpu->clk_shader); - if (IS_ERR(gpu->clk_shader)) - return PTR_ERR(gpu->clk_shader); - gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + err = etnaviv_gpu_clk_get(gpu); + if (err) + return err; /* TODO: figure out max mapped size */ dev_set_drvdata(dev, gpu);