Message ID | 20230615111649.36344-3-amit.kumar-mahapatra@amd.com |
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State | New |
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Thu, 15 Jun 2023 06:17:04 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Thu, 15 Jun 2023 04:17:04 -0700 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Thu, 15 Jun 2023 06:17:00 -0500 From: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> To: <tudor.ambarus@linaro.org>, <pratyush@kernel.org>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <git@amd.com>, <michael@walle.cc>, <linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <amitrkcian2002@gmail.com>, Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Subject: [PATCH 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP signal not connected Date: Thu, 15 Jun 2023 16:46:49 +0530 Message-ID: <20230615111649.36344-3-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com> References: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT103:EE_|SA3PR12MB8802:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ae19120-460b-40a2-1693-08db6d920ce0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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mtd: spi-nor: Avoid setting SRWD bit in SR
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Commit Message
Mahapatra, Amit Kumar
June 15, 2023, 11:16 a.m. UTC
Setting the status register write disable (SRWD) bit in the status
register (SR) with WP signal of the flash not connected will configure the
SR permanently as read-only. If WP signal is not connected, avoid setting
SRWD bit while writing the SR during flash protection.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
drivers/mtd/spi-nor/core.c | 3 +++
drivers/mtd/spi-nor/core.h | 1 +
drivers/mtd/spi-nor/swp.c | 5 +++--
3 files changed, 7 insertions(+), 2 deletions(-)
Comments
Am 2023-06-15 13:16, schrieb Amit Kumar Mahapatra: > Setting the status register write disable (SRWD) bit in the status > register (SR) with WP signal of the flash not connected will configure > the > SR permanently as read-only. If WP signal is not connected, avoid > setting > SRWD bit while writing the SR during flash protection. > > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> > --- > drivers/mtd/spi-nor/core.c | 3 +++ > drivers/mtd/spi-nor/core.h | 1 + > drivers/mtd/spi-nor/swp.c | 5 +++-- > 3 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 0bb0ad14a2fc..81b57c51f41c 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor > *nor) > if (flags & NO_CHIP_ERASE) > nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; > > + if (of_property_read_bool(np, "broken-wp")) > + nor->flags |= SNOR_F_BROKEN_WP; > + > if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 && > !nor->controller_ops) > nor->flags |= SNOR_F_RWW; > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 4fb5ff09c63a..6ac932eba913 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -132,6 +132,7 @@ enum spi_nor_option_flags { > SNOR_F_SWP_IS_VOLATILE = BIT(13), > SNOR_F_RWW = BIT(14), > SNOR_F_ECC = BIT(15), > + SNOR_F_BROKEN_WP = BIT(16), > }; > > struct spi_nor_read_command { > diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c > index 0ba716e84377..074f3bce2034 100644 > --- a/drivers/mtd/spi-nor/swp.c > +++ b/drivers/mtd/spi-nor/swp.c > @@ -214,8 +214,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > > status_new = (status_old & ~mask & ~tb_mask) | val; > > - /* Disallow further writes if WP pin is asserted */ > - status_new |= SR_SRWD; > + /* Disallow further writes if WP pin is connected */ "is not broken" or similar. Maybe descibe what is broken. Like I said, this might also be a valid use case. Thinking more about this, maybe we should make this configurable. I.e. make it possible to set the locking region without disabling further writes. Although I'm not sure how. Right now, we always enable both the software and hardware write protection. (winbond distiguish between software and hardware write protection here; software here means not linux/kernel but just setting the protection bits without the locking bit). And in the case WP# is tied to low, one should not use the hardware write protection. Although I'm not really sure, how to do that in a backwards compatible way. -michael
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0bb0ad14a2fc..81b57c51f41c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) if (flags & NO_CHIP_ERASE) nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; + if (of_property_read_bool(np, "broken-wp")) + nor->flags |= SNOR_F_BROKEN_WP; + if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 && !nor->controller_ops) nor->flags |= SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 4fb5ff09c63a..6ac932eba913 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -132,6 +132,7 @@ enum spi_nor_option_flags { SNOR_F_SWP_IS_VOLATILE = BIT(13), SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), + SNOR_F_BROKEN_WP = BIT(16), }; struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 0ba716e84377..074f3bce2034 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -214,8 +214,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) status_new = (status_old & ~mask & ~tb_mask) | val; - /* Disallow further writes if WP pin is asserted */ - status_new |= SR_SRWD; + /* Disallow further writes if WP pin is connected */ + if (!(nor->flags & SNOR_F_BROKEN_WP)) + status_new |= SR_SRWD; if (!use_top) status_new |= tb_mask;