From patchwork Wed Jun 14 11:59:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5ZCV5bu65rCR?= X-Patchwork-Id: 107926 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1198849vqr; Wed, 14 Jun 2023 05:12:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4T+Yqpn/wFdHFsGRHuqC03TE5p8UxPC2pA7BADQVo6Tbp2uNNk3yHZY4B3pAX1gVPxmK8O X-Received: by 2002:a05:6a00:a93:b0:653:deba:204b with SMTP id b19-20020a056a000a9300b00653deba204bmr1969458pfl.9.1686744779635; Wed, 14 Jun 2023 05:12:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686744779; cv=none; d=google.com; s=arc-20160816; b=kO0gLjJo7cNg1ciK/3qL6d9F/7Bq9iEWOs48PBjFzGLA4stfjys0Paa9I2dUMzxp2s mVyRqNyBqASxeACG2QX4j1e+CgQHo10qD5WN62CRRQoQ0fU4ZF+E4r8Vuc0T7zyZOT4a 0MvNiUPYSj057p3AJuFbn+SdhzoXLn3H0EKFAoYeTaFDbbwdcknMynmon0AydvbVLTRW vy0eNAsox6xqEHOn7JtOEaPCNbc2ddEtr8l+1+H3+0Uv/5yfNdRuwhPoIb20ov5twSWG v0F9Oasg8HFcaqpQRbLXWqU/kW5Nfln38hx0hVzVAAEDwnTxex1iMt/P9Lj3+XWXLnsf oaqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=39DJ7VWufD2H2f/H86ulfsNKT1ceZyg+gHLfc1uUI94=; b=nrvfv8GkbFQPQUQQGF/eXrNSAgeGBKkZ51QAG+6fWLDKpBTS7vUoGy+Eiw8wxEp0Si 0/zTJL1quERKfc25tZIuIJBCYJzlj3IkFSAwyvalD5cw7kZXBa7P/QiTdcpCACcHlxac IIe0Gw+UlU22yZNmX6nA9i2OHCiH64ShVRAOEDOl1v2ds/1WN2ffKgIBD4IWyto+2U6e IaihklS/n/iN+xitVdSve77rWBq+cI4s+k/JDSo2lUli9sT2gPhzqzburJVj6fZClgGN /k7TzDwH890Ywpm63CLlT+h/t59JB4PBOhyXKz6TSO8UX1FYJ9mjisycTm7Y8bPpijQ8 bupg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x26-20020aa7941a000000b0064f98fbcac8si10848021pfo.293.2023.06.14.05.12.44; Wed, 14 Jun 2023 05:12:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244344AbjFNMAM (ORCPT + 99 others); Wed, 14 Jun 2023 08:00:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244385AbjFNL7q (ORCPT ); Wed, 14 Jun 2023 07:59:46 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E4A4E1FFC; Wed, 14 Jun 2023 04:59:39 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.116]) by gateway (Coremail) with SMTP id _____8DxRumqq4lksx0FAA--.8960S3; Wed, 14 Jun 2023 19:59:38 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.42.116]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxNeSoq4lkzJMaAA--.10424S3; Wed, 14 Jun 2023 19:59:37 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen , WANG Xuerui , loongson-kernel@lists.loongnix.cn, stable@vger.kernel.org, liuyun Subject: [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register Date: Wed, 14 Jun 2023 19:59:32 +0800 Message-Id: <20230614115936.5950-2-lvjianmin@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230614115936.5950-1-lvjianmin@loongson.cn> References: <20230614115936.5950-1-lvjianmin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxNeSoq4lkzJMaAA--.10424S3 X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxJr1DZFy8WFyfXr1fXF1xtFc_yoW8tw15pa yaqa1avr4UJr1UKF1kGayrXFy3J39xC39rKayYyr1fXwn8C3sFkrsrA3W8ZFWxCrWUZF13 ZrWSyF18C3W5AFcCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUB2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWr XwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwI xGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26F4j6r4UJwCI42IY6I8E87Iv6xkF7I0E 14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU7aZXUUUUU X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768680094048589067?= X-GMAIL-MSGID: =?utf-8?q?1768680094048589067?= In an ACPI-based dual-bridge system, IRQ of each bridge's PCH PIC sent to CPU is always a zero-based number, which means that the IRQ on PCH PIC of each bridge is mapped into vector range from 0 to 63 of upstream irqchip(e.g. EIOINTC). EIOINTC N: [0 ... 63 | 64 ... 255] -------- ---------- ^ ^ | | PCH PIC N | PCH MSI N For example, the IRQ vector number of sata controller on PCH PIC of each bridge is 16, which is sent to upstream irqchip of EIOINTC when an interrupt occurs, which will set bit 16 of EIOINTC. Since hwirq of 16 on EIOINTC has been mapped to a irq_desc for sata controller during hierarchy irq allocation, the related mapped IRQ will be found through irq_resolve_mapping() in the IRQ domain of EIOINTC. So, the IRQ number set in HT vector register should be fixed to be a zero-based number. Cc: stable@vger.kernel.org Reviewed-by: Huacai Chen Co-developed-by: liuyun Signed-off-by: liuyun Signed-off-by: Jianmin Lv --- drivers/irqchip/irq-loongson-pch-pic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index e5fe4d50be05..921c5c0190d1 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -401,14 +401,12 @@ static int __init acpi_cascade_irqdomain_init(void) int __init pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic) { - int ret, vec_base; + int ret; struct fwnode_handle *domain_handle; if (find_pch_pic(acpi_pchpic->gsi_base) >= 0) return 0; - vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ; - domain_handle = irq_domain_alloc_fwnode(&acpi_pchpic->address); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); @@ -416,7 +414,7 @@ int __init pch_pic_acpi_init(struct irq_domain *parent, } ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size, - vec_base, parent, domain_handle, acpi_pchpic->gsi_base); + 0, parent, domain_handle, acpi_pchpic->gsi_base); if (ret < 0) { irq_domain_free_fwnode(domain_handle);