Message ID | 20230614065949.146187-3-anshuman.khandual@arm.com |
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State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1054431vqr; Wed, 14 Jun 2023 00:18:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4l9zLJrsesKCqbKHLzOZA+5BDtylzAWXqEqrFYxHxoLPaH+p62xcy60KKi56Zs/Mbi64T6 X-Received: by 2002:a2e:980c:0:b0:2b3:49e0:964 with SMTP id a12-20020a2e980c000000b002b349e00964mr377779ljj.40.1686727118466; Wed, 14 Jun 2023 00:18:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686727118; cv=none; d=google.com; s=arc-20160816; b=U023g7L66u25/cjN+tzYYspOGmMoF3aD8BIRUlzv20mBWqB0FPK6j53KIIcWip+5z7 h3cmL6673P7yANyp/EFM7msugnvMIPB7r0GexuUHL28J4gidx3cFf2ug9HGxMDet3E5M dWjQMJnQm08qFI6fP3EYPM6WnMODnuvP3YhEEpjnF6ODfAMRFXVCqbmgi5uOXr2UZPxM EyKGzExliqXJWjifV9GUYtySbjt7D81cRoufHy+k5nNpg3QCtpOyzoim+oXsce6nQgBI 4O8QSWx5dgBcxSsWLVxQNCfbSPyKgph42wIrl4U9lh5zCRxsoFzt+TG7k1s7VTsi7Ju4 l94Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=c8tuB4cHL0fZ9JgdKKa3Ty8vxlhryF/LDWYP7lX7IBo=; b=H8pHwS9TQ6hRGcCRADtDltknv9hlzBewO0p4uZPZmRsYoJySnmfJ3gE82bTckuOdXD aNQnGerBkPpSUWgcl+4hp8ca4PUvhUVfULrJDJev69JZxSxATphsRXfBJG9dqIXry2cv 2UCkmMJoeSaH50nQ3caTjJzuFsmOOgSgndRa+HbZLVDlL0ZUBeRnvh4wdOO0mvTkcngM zNNc9CNTHFP7og+S4Hc9h6QkfsKFuV27sHOuk3TSTvbhgSzYcaB2XOxnDheb7wDba9aL GksETM6Te+5bO7oOfn4aEfBvXLbG0n99QIYH4LkHk6BvvAmY8Zf7mkkGWO1V7Ej5yGgg ThHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a22-20020aa7d916000000b005149135a97csi8749576edr.272.2023.06.14.00.18.12; Wed, 14 Jun 2023 00:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242572AbjFNHAZ (ORCPT <rfc822;jesperjuhl76@gmail.com> + 99 others); Wed, 14 Jun 2023 03:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238550AbjFNHAU (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 14 Jun 2023 03:00:20 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7A2AF198D for <linux-kernel@vger.kernel.org>; Wed, 14 Jun 2023 00:00:18 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDF51152B; Wed, 14 Jun 2023 00:01:02 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.15]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F374B3F663; Wed, 14 Jun 2023 00:00:13 -0700 (PDT) From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, broonie@kernel.org Cc: Anshuman Khandual <anshuman.khandual@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh@kernel.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, James Morse <james.morse@arm.com>, kvmarm@lists.linux.dev, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 02/14] arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools format Date: Wed, 14 Jun 2023 12:29:37 +0530 Message-Id: <20230614065949.146187-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614065949.146187-1-anshuman.khandual@arm.com> References: <20230614065949.146187-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768661574923735919?= X-GMAIL-MSGID: =?utf-8?q?1768661574923735919?= |
Series |
arm64/sysreg: Convert TRBE registers to automatic generation
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Commit Message
Anshuman Khandual
June 14, 2023, 6:59 a.m. UTC
This renames TRBPTR_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1be3a44b8289..b7a0d7d0f4d6 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -260,8 +260,8 @@ #define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1) #define TRBLIMITR_EL1_FM_SHIFT 1 #define TRBLIMITR_EL1_E BIT(0) -#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) -#define TRBPTR_PTR_SHIFT 0 +#define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) +#define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) #define TRBBASER_BASE_SHIFT 12 #define TRBSR_EC_MASK GENMASK(5, 0)