From patchwork Wed Jun 14 02:47:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sui Jingfeng <15330273260@189.cn> X-Patchwork-Id: 107682 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp966868vqr; Tue, 13 Jun 2023 20:09:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7e2N8cVHDImn7IHbAgFMTtA60C6y0A535IXOV2So4g61Dc6LdWzAqfOt8wEmQbSTZwK9FT X-Received: by 2002:a17:907:a414:b0:965:b087:8002 with SMTP id sg20-20020a170907a41400b00965b0878002mr15413545ejc.0.1686712194189; Tue, 13 Jun 2023 20:09:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686712194; cv=none; d=google.com; s=arc-20160816; b=QffMKcz+4bYkY0dqU3qmrUAix6PFZit7eC3Y+fFkkLD6mfSiWvfscuS1NIAws3nVcT Nuvg1eXbg4RHQhdBkppAe+4xUeIfnpvcAKCvIwKsRpZw+1qgzEy55LqKRTJc20vh6M/I Cj8qExBWIdQf8gGkgcHMIAkLYpwtNMxNfMcmBrkkvdDt/ST4qS3z+jmBCRb5kCzcAoGW 8Qko3tUaMF2sIprPqoukpoHQZmUpC7amfCojMNhHkJh4shBoPJszP0NGBou1LkUgDuKV 9a/BygVVGvPKBKd5cvfcizLGDC2RMejZStLHlF85VvuVUbFNHolniBQU3B4gVFr9PAdX jKrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:sender :hmm_source_type:hmm_attache_num:hmm_source_ip; bh=ryQxEOEn5nxGeynRYQSiZwrj9tClDnH39O24gmV1Ywk=; b=ymDLv4Kh9M5r6eu/O6mx5oi3zYp8VoYK6HVlOr7DCUgJhIeYZC8ZMfiQIdtD/gg4/I NgBytlibRj4qZnuJaG4R/giRsH1nl+O89rxSGl3GVZr8g5jFa1AJNAZnMqnVxsp3WxDw I2uVubz2z8yVXu0twfOrMJU5cxlT79Hu4FlHxTriDMfVQYihnu76+8ICbtPHUZoZ/hfH 0VMwEHcUXV8YmQcniEt0fFlnU3kRmgwer/36p8l7FuFKlf/vv2YyocVSheGr5MN74fS6 ISMzsEgobtfZbl1TSzoczeHVXavfO1nk06ItfeMnjshSJuxWum5iYcUVtEbHZQLyzXf1 KuPw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n4-20020a1709061d0400b00977c72ac5d2si7320636ejh.468.2023.06.13.20.09.30; Tue, 13 Jun 2023 20:09:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242141AbjFNCs2 (ORCPT + 99 others); Tue, 13 Jun 2023 22:48:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242198AbjFNCsG (ORCPT ); Tue, 13 Jun 2023 22:48:06 -0400 Received: from 189.cn (ptr.189.cn [183.61.185.104]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 12D661BE9 for ; Tue, 13 Jun 2023 19:47:59 -0700 (PDT) HMM_SOURCE_IP: 10.64.8.31:39796.1729481184 HMM_ATTACHE_NUM: 0000 HMM_SOURCE_TYPE: SMTP Received: from clientip-114.242.206.180 (unknown [10.64.8.31]) by 189.cn (HERMES) with SMTP id 56F9A102A0A; Wed, 14 Jun 2023 10:47:57 +0800 (CST) Received: from ([114.242.206.180]) by gateway-151646-dep-75648544bd-xp9j7 with ESMTP id 9bcf566c75864b53860340869d884dc2 for l.stach@pengutronix.de; Wed, 14 Jun 2023 10:47:59 CST X-Transaction-ID: 9bcf566c75864b53860340869d884dc2 X-Real-From: 15330273260@189.cn X-Receive-IP: 114.242.206.180 X-MEDUSA-Status: 0 Sender: 15330273260@189.cn From: Sui Jingfeng <15330273260@189.cn> To: Lucas Stach , Christian Gmeiner , Daniel Vetter , Bjorn Helgaas Cc: linux-kernel@vger.kernel.org, etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, loongson-kernel@lists.loongnix.cn, Sui Jingfeng Subject: [PATCH v9 9/9] drm/etnaviv: Clean up etnaviv_pdev_probe() function Date: Wed, 14 Jun 2023 10:47:45 +0800 Message-Id: <20230614024745.865129-10-15330273260@189.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614024745.865129-1-15330273260@189.cn> References: <20230614024745.865129-1-15330273260@189.cn> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,FROM_LOCAL_DIGITS, FROM_LOCAL_HEX,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768645926025958096?= X-GMAIL-MSGID: =?utf-8?q?1768645926025958096?= From: Sui Jingfeng Add a dedicate function to do the DMA configuration to the virtual master. Also replace the &pdev->dev with dev. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 65 +++++++++++++++------------ 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 0ee7f641cee3..df4c21a17d9d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -54,6 +54,40 @@ static bool etnaviv_is_dma_coherent(struct device *dev) return coherent; } +static int etnaviv_of_dma_configure(struct device *dev) +{ + struct device_node *first_node; + + /* + * PTA and MTLB can have 40 bit base addresses, but + * unfortunately, an entry in the MTLB can only point to a + * 32 bit base address of a STLB. Moreover, to initialize the + * MMU we need a command buffer with a 32 bit address because + * without an MMU there is only an indentity mapping between + * the internal 32 bit addresses and the bus addresses. + * + * To make things easy, we set the dma_coherent_mask to 32 + * bit to make sure we are allocating the command buffers and + * TLBs in the lower 4 GiB address space. + */ + if (dma_set_mask(dev, DMA_BIT_MASK(40)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) { + dev_err(dev, "No suitable DMA available\n"); + return -ENODEV; + } + + /* + * Apply the same DMA configuration to the virtual etnaviv + * device as the GPU we found. This assumes that all Vivante + * GPUs in the system share the same DMA constraints. + */ + first_node = etnaviv_of_first_available_node(); + if (first_node) + of_dma_configure(dev, first_node, true); + + return 0; +} + /* * etnaviv private data construction and destructions: */ @@ -663,7 +697,6 @@ static const struct component_master_ops etnaviv_master_ops = { static int etnaviv_pdev_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *first_node = NULL; struct component_match *match = NULL; if (!dev->platform_data) { @@ -673,10 +706,7 @@ static int etnaviv_pdev_probe(struct platform_device *pdev) if (!of_device_is_available(core_node)) continue; - if (!first_node) - first_node = core_node; - - drm_of_component_match_add(&pdev->dev, &match, + drm_of_component_match_add(dev, &match, component_compare_of, core_node); } } else { @@ -687,31 +717,8 @@ static int etnaviv_pdev_probe(struct platform_device *pdev) component_match_add(dev, &match, component_compare_dev_name, names[i]); } - /* - * PTA and MTLB can have 40 bit base addresses, but - * unfortunately, an entry in the MTLB can only point to a - * 32 bit base address of a STLB. Moreover, to initialize the - * MMU we need a command buffer with a 32 bit address because - * without an MMU there is only an indentity mapping between - * the internal 32 bit addresses and the bus addresses. - * - * To make things easy, we set the dma_coherent_mask to 32 - * bit to make sure we are allocating the command buffers and - * TLBs in the lower 4 GiB address space. - */ - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)) || - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { - dev_dbg(&pdev->dev, "No suitable DMA available\n"); + if (etnaviv_of_dma_configure(dev)) return -ENODEV; - } - - /* - * Apply the same DMA configuration to the virtual etnaviv - * device as the GPU we found. This assumes that all Vivante - * GPUs in the system share the same DMA constraints. - */ - if (first_node) - of_dma_configure(&pdev->dev, first_node, true); return component_master_add_with_match(dev, &etnaviv_master_ops, match); }