[-next,3/3] clk: tegra: Fix unsigned comparison with less than zero
Commit Message
The return value of the round_rate() is long. However, the
return value is being assigned to an unsigned long variable
'rate', so making 'rate' to long.
silence the warnings:
./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
drivers/clk/tegra/clk-periph.c | 2 +-
drivers/clk/tegra/clk-super.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Comments
Quoting Yang Li (2023-06-13 18:29:13)
> The return value of the round_rate() is long. However, the
> return value is being assigned to an unsigned long variable
> 'rate', so making 'rate' to long.
>
> silence the warnings:
> ./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> ./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
> drivers/clk/tegra/clk-periph.c | 2 +-
> drivers/clk/tegra/clk-super.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Instead of this can you implement determine_rate() for div_ops?
@@ -51,7 +51,7 @@ static int clk_periph_determine_rate(struct clk_hw *hw,
struct tegra_clk_periph *periph = to_clk_periph(hw);
const struct clk_ops *div_ops = periph->div_ops;
struct clk_hw *div_hw = &periph->divider.hw;
- unsigned long rate;
+ long rate;
__clk_hw_set_clk(div_hw, hw);
@@ -147,7 +147,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
{
struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
struct clk_hw *div_hw = &super->frac_div.hw;
- unsigned long rate;
+ long rate;
__clk_hw_set_clk(div_hw, hw);