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Tue, 13 Jun 2023 09:12:36 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 2/3] x86/mce: Define amd_mce_usable_address() Date: Tue, 13 Jun 2023 09:11:41 -0500 Message-ID: <20230613141142.36801-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|PH7PR12MB8156:EE_ X-MS-Office365-Filtering-Correlation-Id: d4097d72-9aac-47d9-b85b-08db6c183e8a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fYpa3JzSgr4HAOSTtVq44TNA5cNBwje1LLqM/uvhe/jBPBA2Pxc4IMcToM/U3LsVdRjlXqLSV9x1QeC8j6+Qu059bAS9on4cAWyj7SVR2xKj7EehmBqRVxvdYKofEwDASXklHivZ94mNIinbpTK8Tv44gyK7WMQEunNW8yfak1JxB/JvEu+U+1Z/cAy4VHjHH5jBhSXevHed0dU7JYzfzgp7Ww0+MWavPu1/auD18LXnIGTINTU9iRuGNkXsDTOKzT7r4JhYxVpw3N6o2ggEiSSWr2huqyEiuqhaCwZ88QvNVq5uqzw8YoDrTBhOoopUAnIe+KjmTptC9O30U8BRI2DUfSsauoxJCzjO+a4T4k3aOKvGhmS+Di/VYcnWiYSUA1ozIzY+NaJ5vrArSh/+4ioKnkiAruJMyT+YHLMhiEeh0/lMYn+8CbWP6tndFx5Ya8mkJYmixVdR4I0i72BAvv8GuLLg5pnrn1HsASxy2z+GRAnyJ8NDrXILDotAeEl556q7bG9Mbx6aworipHTkzBUImdKkQ+uWAmldgVLV+h3UFGR3tv8yY/ZkvDOFxxKPCeMU3gP19OZ7EO6AzXi8URq4Tr8EMepZIzwbgTDLlM1/rFPwn4zo+kg7gXws/2mdy97H805/EBqbAXpsdwQICESjvc3BOKgmDjVLUauAnwPb+QwOuH9MWu1EEz3bGF9k4eUCf0LS0cEz3msj7GEboMpdLRupp5hmyjr74X1XUXZ2oEJ6FGkYQyoP7VfUrsVHFqnHLhjVllZ/BrMl9oHdXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(40470700004)(36840700001)(7696005)(316002)(40460700003)(41300700001)(336012)(83380400001)(426003)(86362001)(82310400005)(36860700001)(2616005)(186003)(26005)(1076003)(44832011)(47076005)(2906002)(16526019)(82740400003)(81166007)(40480700001)(356005)(5660300002)(36756003)(8936002)(8676002)(70206006)(70586007)(478600001)(54906003)(6666004)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; 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However, this is not correct in most cases. Notifiers expecting usable addresses may then operate on inappropriate values. Define a helper function to do AMD-specific checks for a usable memory address. List out all known cases. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 38 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 43 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1ccfb0c9257f..ca79fa10b844 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -746,6 +746,44 @@ bool amd_mce_is_memory_error(struct mce *m) return legacy_mce_is_memory_error(m); } +/* + * AMD systems do not have an explicit indicator that the value in MCA_ADDR is + * a system physical address. Therefore individual cases need to be detected. + * Future cases and checks will be added as needed. + * + * 1) General case + * a) Assume address is not usable. + * 2) "Poison" errors + * a) Indicated by MCA_STATUS[43]: POISON. Defined for all banks except legacy + * Northbridge (bank 4). + * b) Refers to poison consumption in the Core. Does not include "no action", + * "action optional", or "deferred" error severities. + * c) Will include a usuable address so that immediate action can be taken. + * 3) Northbridge DRAM ECC errors + * a) Reported in legacy bank 4 with XEC 8. + * b) MCA_STATUS[43] is *not* defined as POISON in legacy bank 4. Therefore, + * this bit should not be checked. + * + * NOTE: SMCA UMC memory errors fall into case #1. + */ +bool amd_mce_usable_address(struct mce *m) +{ + /* Check special Northbridge case first. */ + if (!mce_flags.smca) { + if (legacy_mce_is_memory_error(m)) + return true; + else if (m->bank == 4) + return false; + } + + /* Check Poison bit for all other bank types. */ + if (m->status & MCI_STATUS_POISON) + return true; + + /* Assume address is not usable for all others. */ + return false; +} + static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 89e2aab5d34d..859ce20dd730 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -464,6 +464,9 @@ int mce_usable_address(struct mce *m) if (!(m->status & MCI_STATUS_ADDRV)) return 0; + if (m->cpuvendor == X86_VENDOR_AMD) + return amd_mce_usable_address(m); + /* Checks after this one are Intel/Zhaoxin-specific: */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index d2412ce2d312..0d4c5b83ed93 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -207,6 +207,7 @@ extern bool filter_mce(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); +bool amd_mce_usable_address(struct mce *m); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -234,6 +235,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m) #else static inline bool amd_filter_mce(struct mce *m) { return false; } +static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } #endif