Message ID | 20230612092355.87937-15-brgl@bgdev.pl |
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Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Giuseppe Cavallaro <peppe.cavallaro@st.com>, Alexandre Torgue <alexandre.torgue@foss.st.com>, Jose Abreu <joabreu@synopsys.com> Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Subject: [PATCH 14/26] net: stmmac: dwmac-qcom-ethqos: add optional phyaux clock Date: Mon, 12 Jun 2023 11:23:43 +0200 Message-Id: <20230612092355.87937-15-brgl@bgdev.pl> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612092355.87937-1-brgl@bgdev.pl> References: <20230612092355.87937-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768490108401465954?= X-GMAIL-MSGID: =?utf-8?q?1768490108401465954?= |
Series |
arm64: qcom: sa8775p-ride: enable the first ethernet port
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Commit Message
Bartosz Golaszewski
June 12, 2023, 9:23 a.m. UTC
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> On sa8775p we don't use the RGMII clock but have an additional PHYAUX clock so add support for it to the driver. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
Comments
On Mon, Jun 12, 2023 at 11:23:43AM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > On sa8775p we don't use the RGMII clock but have an additional PHYAUX > clock so add support for it to the driver. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > index 252dca400071..2f6b9b419601 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > @@ -94,6 +94,7 @@ struct qcom_ethqos { > > unsigned int rgmii_clk_rate; > struct clk *rgmii_clk; > + struct clk *phyaux_clk; > struct phy *serdes_phy; > unsigned int speed; > > @@ -604,6 +605,13 @@ static int ethqos_clks_config(void *priv, bool enabled) > return ret; > } > > + ret = clk_prepare_enable(ethqos->phyaux_clk); > + if (ret) { > + clk_disable_unprepare(ethqos->rgmii_clk); > + dev_err(ðqos->pdev->dev, "phyaux enable failed\n"); > + return ret; > + } > + > /* Enable functional clock to prevent DMA reset to timeout due > * to lacking PHY clock after the hardware block has been power > * cycled. The actual configuration will be adjusted once > @@ -611,6 +619,7 @@ static int ethqos_clks_config(void *priv, bool enabled) > */ > ethqos_set_func_clk_en(ethqos); > } else { > + clk_disable_unprepare(ethqos->phyaux_clk); > clk_disable_unprepare(ethqos->rgmii_clk); > } > > @@ -669,6 +678,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > goto out_config_dt; > } > > + ethqos->phyaux_clk = devm_clk_get_optional(dev, "phyaux"); > + if (IS_ERR(ethqos->phyaux_clk)) { > + ret = PTR_ERR(ethqos->phyaux_clk); > + goto out_config_dt; > + } > + Similar comment to the prior patch about whether or not this should be optional (or selected via platform compatible and required), otherwise looks good. > ret = ethqos_clks_config(ethqos, true); > if (ret) > goto out_config_dt; > -- > 2.39.2 >
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 252dca400071..2f6b9b419601 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -94,6 +94,7 @@ struct qcom_ethqos { unsigned int rgmii_clk_rate; struct clk *rgmii_clk; + struct clk *phyaux_clk; struct phy *serdes_phy; unsigned int speed; @@ -604,6 +605,13 @@ static int ethqos_clks_config(void *priv, bool enabled) return ret; } + ret = clk_prepare_enable(ethqos->phyaux_clk); + if (ret) { + clk_disable_unprepare(ethqos->rgmii_clk); + dev_err(ðqos->pdev->dev, "phyaux enable failed\n"); + return ret; + } + /* Enable functional clock to prevent DMA reset to timeout due * to lacking PHY clock after the hardware block has been power * cycled. The actual configuration will be adjusted once @@ -611,6 +619,7 @@ static int ethqos_clks_config(void *priv, bool enabled) */ ethqos_set_func_clk_en(ethqos); } else { + clk_disable_unprepare(ethqos->phyaux_clk); clk_disable_unprepare(ethqos->rgmii_clk); } @@ -669,6 +678,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev) goto out_config_dt; } + ethqos->phyaux_clk = devm_clk_get_optional(dev, "phyaux"); + if (IS_ERR(ethqos->phyaux_clk)) { + ret = PTR_ERR(ethqos->phyaux_clk); + goto out_config_dt; + } + ret = ethqos_clks_config(ethqos, true); if (ret) goto out_config_dt;