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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bm18-20020a656e92000000b0053074c54c3fsi1922039pgb.868.2023.06.08.19.25.44; Thu, 08 Jun 2023 19:25:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236922AbjFICU4 (ORCPT + 99 others); Thu, 8 Jun 2023 22:20:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbjFICUx (ORCPT ); Thu, 8 Jun 2023 22:20:53 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A973F210E; Thu, 8 Jun 2023 19:20:50 -0700 (PDT) Received: from loongson.cn (unknown [10.2.9.158]) by gateway (Coremail) with SMTP id _____8BxKuqAjIJkldgAAA--.2683S3; Fri, 09 Jun 2023 10:20:48 +0800 (CST) Received: from kvm-1-158.loongson.cn (unknown [10.2.9.158]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxbMp_jIJkDnwJAA--.20801S2; Fri, 09 Jun 2023 10:20:47 +0800 (CST) From: Bibo Mao To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Huacai Chen , Will Deacon , loongarch@lists.linux.dev, loongson-kernel@lists.loongnix.cn Subject: [PATCH v4] PCI: Align pci memory space base address with page size Date: Fri, 9 Jun 2023 10:20:47 +0800 Message-Id: <20230609022047.2195689-1-maobibo@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxbMp_jIJkDnwJAA--.20801S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxGr1rurW3JF48uF4UArWkAFc_yoW5Gr15pF y3A3ZrCrW8Kr1fJ3yDt34kuFZxXan2g3yYvryfCas3GFnrZF9rCw1kAry2qFyUCr4kGryj qFn5KF15Xay5XagCm3ZEXasCq-sJn29KB7ZKAUJUUUUr529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUU9Fb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2 xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_ Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x 0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km07C267AK xVWUXVWUAwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2 KfnxnUUI43ZEXa7IU8hiSPUUUUU== X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768190175677254713?= X-GMAIL-MSGID: =?utf-8?q?1768190175677254713?= Some PCI devices have only 4K memory space size, it is normal in general machines and aligned with page size. However some architectures which support different page size, default page size on LoongArch is 16K, and ARM64 supports page size varying from 4K to 64K. On machines where larger page size is use, memory space region of two different pci devices may be in one page. It is not safe with mmu protection, also VFIO pci device driver requires base address of pci memory space page aligned, so that it can be memory mapped to qemu user space when it is passed-through to vm. It consumes more pci memory resource with page size alignment requirement, here extra option PCI_MEMRES_PAGE_ALIGN is added, it can be enabled by different architectures. Signed-off-by: Bibo Mao Reviewed-by: Huacai Chen --- Change history v4: add extra kernel option PCI_MEMRES_PAGE_ALIGN to set memory resource page aligned. v3: move alignment requirement to generic pci code v2: add pci resource alignment requirement in arch specified function pcibios_align_resource on arm64/LoongArch platforms --- arch/loongarch/Kconfig | 1 + drivers/pci/Kconfig | 3 +++ drivers/pci/setup-res.c | 7 +++++++ 3 files changed, 11 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index d38b066fc931..65b2f6ba9f8e 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -142,6 +142,7 @@ config LOONGARCH select PCI_LOONGSON select PCI_MSI_ARCH_FALLBACKS select PCI_QUIRKS + select PCI_MEMRES_PAGE_ALIGN select PERF_USE_VMALLOC select RTC_LIB select SMP diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 9309f2469b41..9be5f85ff9dc 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -128,6 +128,9 @@ config PCI_LOCKLESS_CONFIG config PCI_BRIDGE_EMUL bool +config PCI_MEMRES_PAGE_ALIGN + bool + config PCI_IOV bool "PCI IOV support" select PCI_ATS diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 967f9a758923..6ad76734a670 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -339,6 +339,13 @@ int pci_assign_resource(struct pci_dev *dev, int resno) return -EINVAL; } +#ifdef CONFIG_PCI_MEMRES_PAGE_ALIGN + /* + * force minimum page alignment for vfio pci usage + */ + if (res->flags & IORESOURCE_MEM) + align = max_t(resource_size_t, PAGE_SIZE, align); +#endif size = resource_size(res); ret = _pci_assign_resource(dev, resno, size, align);