Message ID | 20230608070017.28072-2-raag.jadav@intel.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp92287vqr; Thu, 8 Jun 2023 00:06:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5vCFonzuX4/oKxLYvDEyNF0kWoUFhN9ZMBVoe2aGqWIZa9PG29ZdP07vYwQUnfgGkqjHUe X-Received: by 2002:a05:6358:bba5:b0:129:be5b:fff with SMTP id df37-20020a056358bba500b00129be5b0fffmr6162376rwb.9.1686207960571; Thu, 08 Jun 2023 00:06:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686207960; cv=none; d=google.com; s=arc-20160816; b=tNGrxwUPbYWQ/iP1yW+uFUHzL0h2HE1TckvIE73RT3BkHfcBfwKCZr0Y4F3BAftDDf 7yfm9FfUoTOXf5qM7D7JF0PGjGWbPdtdiTwzIoSB6HaJFUPLKbvzgch3FLUeqhUPx+bO hhb1cbcg1Ju9Ht7gExQkVoD4f6hr6L/sWGb0DG8siAvi5A7LZF+htC3HgHNEx3uYcUqi 3wYuekJZU4Uv29hxShmIelld6Zloq+Ml7DYrbX5/0Zm4M7O13ftIXfGcrr+lwzHv3wl1 ++tDEDeFQ8abJf3oAo34D3YsXysc4KwAt4XU0LTV5NaK05bbXTu7uGnkQjgBwbADGKGR 7w6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Lpa+4F6dot7Vr6Y6Gm17X60b5nlO065rdDY8ivQUWUE=; b=Ow+s1O7liq4cLoK4Ef06EAY/jIgWQLvOaWDS7DUDBp44hi4ZFinIV06bC+eyZejXMD WtvhBrkEviJNlZSglIp+qyoc/ow8P0mne1GK0gFfZrQA3vLC1nCsy4ptsIsURjNVBxE2 TT9I5HyRyluqiu0LA0A1eKcj7CjJuxUJCMMZFE5WQowOgGmmZuFy71jLdas0xqVXxk4Q HmZmVmsW4AwCqa9TUemSowR0UX3o2KcuMw2pKHZSjvjvY6f6M/iQJaMmE4SpDd+ScV28 u4nG9ZQ/UhBH4S/7G2dFn8t8dUCFzcK13tWOuonPV2tbJC/yzdL0OGOmvNcBtL6lqkwv eIQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="h5y+/OUJ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j184-20020a638bc1000000b0053efe1af2d0si580496pge.224.2023.06.08.00.05.39; Thu, 08 Jun 2023 00:06:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="h5y+/OUJ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235298AbjFHHCZ (ORCPT <rfc822;liningstudo@gmail.com> + 99 others); Thu, 8 Jun 2023 03:02:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235156AbjFHHCD (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 8 Jun 2023 03:02:03 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBE931BD6; Thu, 8 Jun 2023 00:01:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686207710; x=1717743710; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ef5s9TkcxXSlz6lTIJfajIVYzY4IV1HrFB/BqDVmIJA=; b=h5y+/OUJbTuPmHhSWwAORY3VTXo84225FNXdLYyTIXe42ZxNQwwHXyJD 5fZ4I8FTSmxVotSS2mdYMFBfJis9tMOMrEHkh2PcKhwQupPyZg6fd/H9f NBoAcEM1x6As1sCiowGRU+i+hf8kNL4L8D6Gz3X5u6D3SPKG8v/Lt9Ycs H2LnW8mZMVpZJf7xVr3G4L2bimpEIIHy0SV+nGSB7XwSSHu4+xWRF7uca soRWNr11VbtihbsjZGil371AJX5fqKZMVRC1Qvb4+zDwa3niPXVWVHMV+ 2XzOIgdXzHc9bp15WQzzjTuITA/mju9rS20ypoHOuJxLxLzcNH4Erc3iJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="359696344" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208";a="359696344" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2023 00:01:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="709867969" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208";a="709867969" Received: from inesxmail01.iind.intel.com ([10.223.154.20]) by orsmga002.jf.intel.com with ESMTP; 08 Jun 2023 00:01:07 -0700 Received: from inlubt0316.iind.intel.com (inlubt0316.iind.intel.com [10.191.20.213]) by inesxmail01.iind.intel.com (Postfix) with ESMTP id 0E9AD1AA12; Thu, 8 Jun 2023 12:31:07 +0530 (IST) Received: by inlubt0316.iind.intel.com (Postfix, from userid 12101951) id 089691DE; Thu, 8 Jun 2023 12:31:07 +0530 (IST) From: Raag Jadav <raag.jadav@intel.com> To: linus.walleij@linaro.org, mika.westerberg@linux.intel.com, andriy.shevchenko@linux.intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mallikarjunappa.sangannavar@intel.com, pandith.n@intel.com, Raag Jadav <raag.jadav@intel.com> Subject: [PATCH v1 1/4] pinctrl: intel: optimize set_mux hook Date: Thu, 8 Jun 2023 12:30:14 +0530 Message-Id: <20230608070017.28072-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230608070017.28072-1-raag.jadav@intel.com> References: <20230608070017.28072-1-raag.jadav@intel.com> X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768117198456506948?= X-GMAIL-MSGID: =?utf-8?q?1768117198456506948?= |
Series | Minor optimizations for Intel pinctrl | |
Commit Message
Raag Jadav
June 8, 2023, 7 a.m. UTC
Utilize a temporary variable for common shift operation
inside ->set_mux() hook and save a few bytes.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3)
Function old new delta
intel_pinmux_set_mux 245 242 -3
Total: Before=10472, After=10469, chg -0.03%
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/pinctrl/intel/pinctrl-intel.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
Comments
On Thu, Jun 08, 2023 at 12:30:14PM +0530, Raag Jadav wrote: > Utilize a temporary variable for common shift operation > inside ->set_mux() hook and save a few bytes. > > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3) > Function old new delta > intel_pinmux_set_mux 245 242 -3 > Total: Before=10472, After=10469, chg -0.03% Shouldn't the compiler be able to optimize this if you ask with the -Ox options? I don't really see much benefit for "optimizations" like this. That said using temporary variable here improves readability so this one is acceptable by me. As long as you change the commit message accordingly. > Signed-off-by: Raag Jadav <raag.jadav@intel.com> > --- > drivers/pinctrl/intel/pinctrl-intel.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c > index c7a71c49df0a..e8adf2580321 100644 > --- a/drivers/pinctrl/intel/pinctrl-intel.c > +++ b/drivers/pinctrl/intel/pinctrl-intel.c > @@ -411,18 +411,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, > /* Now enable the mux setting for each pin in the group */ > for (i = 0; i < grp->grp.npins; i++) { > void __iomem *padcfg0; > - u32 value; > + u32 value, pmode; > > padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); > - value = readl(padcfg0); > > + value = readl(padcfg0); > value &= ~PADCFG0_PMODE_MASK; > > if (grp->modes) > - value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; > + pmode = grp->modes[i]; > else > - value |= grp->mode << PADCFG0_PMODE_SHIFT; > + pmode = grp->mode; > > + value |= pmode << PADCFG0_PMODE_SHIFT; > writel(value, padcfg0); > } > > -- > 2.17.1
> On Thu, Jun 08, 2023 at 12:30:14PM +0530, Raag Jadav wrote: > > Utilize a temporary variable for common shift operation inside > > ->set_mux() hook and save a few bytes. > > > > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3) > > Function old new delta > > intel_pinmux_set_mux 245 242 -3 > > Total: Before=10472, After=10469, chg -0.03% > > Shouldn't the compiler be able to optimize this if you ask with the -Ox > options? Forgot to add. This is with default -O2. Is it a good idea to mention it? > I don't really see much benefit for "optimizations" like this. That said using > temporary variable here improves readability so this one is acceptable by > me. As long as you change the commit message accordingly.
On Thu, Jun 08, 2023 at 10:20:58AM +0000, Jadav, Raag wrote: > > On Thu, Jun 08, 2023 at 12:30:14PM +0530, Raag Jadav wrote: > > > Utilize a temporary variable for common shift operation inside > > > ->set_mux() hook and save a few bytes. > > > > > > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3) > > > Function old new delta > > > intel_pinmux_set_mux 245 242 -3 > > > Total: Before=10472, After=10469, chg -0.03% > > > > Shouldn't the compiler be able to optimize this if you ask with the -Ox > > options? > > Forgot to add. This is with default -O2. > Is it a good idea to mention it? Yes, I think it is.
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index c7a71c49df0a..e8adf2580321 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -411,18 +411,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, /* Now enable the mux setting for each pin in the group */ for (i = 0; i < grp->grp.npins; i++) { void __iomem *padcfg0; - u32 value; + u32 value, pmode; padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); - value = readl(padcfg0); + value = readl(padcfg0); value &= ~PADCFG0_PMODE_MASK; if (grp->modes) - value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; + pmode = grp->modes[i]; else - value |= grp->mode << PADCFG0_PMODE_SHIFT; + pmode = grp->mode; + value |= pmode << PADCFG0_PMODE_SHIFT; writel(value, padcfg0); }