diff mbox series

[3/4] arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells

Message ID 20230607090653.2468317-4-wenst@chromium.org
State New
Headers
Series arm64: dts: mediatek: mt8186: More DVFS nodes |

Commit Message

Chen-Yu Tsai June 7, 2023, 9:06 a.m. UTC 
  On the MT8186, the chip is binned for different GPU voltages at the
highest OPPs. The binning value is stored in the efuse.

Add the NVMEM cell, and tie it to the GPU.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

AngeloGioacchino Del Regno June 8, 2023, 2:19 p.m. UTC | #1 
Il 07/06/23 11:06, Chen-Yu Tsai ha scritto:
> On the MT8186, the chip is binned for different GPU voltages at the
> highest OPPs. The binning value is stored in the efuse.
> 
> Add the NVMEM cell, and tie it to the GPU.
> 
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 6735c1feb26d..c58d7eb87b1d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1567,6 +1567,11 @@  efuse: efuse@11cb0000 {
 			reg = <0 0x11cb0000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			gpu_speedbin: gpu-speed-bin@59c {
+				reg = <0x59c 0x4>;
+				bits = <0 3>;
+			};
 		};
 
 		mipi_tx0: dsi-phy@11cc0000 {
@@ -1599,6 +1604,8 @@  gpu: gpu@13040000 {
 					<&spm MT8186_POWER_DOMAIN_MFG3>;
 			power-domain-names = "core0", "core1";
 			#cooling-cells = <2>;
+			nvmem-cells = <&gpu_speedbin>;
+			nvmem-cell-names = "speed-bin";
 			status = "disabled";
 		};