From patchwork Sun Jun 4 04:55:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 102936 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1975487vqr; Sat, 3 Jun 2023 21:58:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7LtFQj8BLT6Vmk3WGPfVMaagJGYFYPvYrWNm50rrG4Nd1rL1HhbatyMPEYuAfZPPFfRgBj X-Received: by 2002:a81:92cc:0:b0:565:d3f9:209e with SMTP id j195-20020a8192cc000000b00565d3f9209emr5441409ywg.34.1685854684422; Sat, 03 Jun 2023 21:58:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685854684; cv=none; d=google.com; s=arc-20160816; b=EQzvJi4ibGbajAAw97zsGC7f4olEcMHOO+QAeyNNGrgBmBb5uzgeD6sIFUGVnAtdRZ WHzY7BJ6rxr9Hb6f522ww0U2B0GL/lfDiiHPkt0eG0K/HyjfcPU23UoMmW8QvJG16sTW nRfUziqT1JZhjduLq3h/ftFSQrrqaeoP5TEkbzMKXfbUTLHsBetfLI4hYzoXLZA4Lr3Z MI91c/12ClFJ8BFF5VIe8YZ3i4XXIzoIrmPJAeO9I62ELvGhKlOHeEOiAg6bDUTK/AbE 6J/+G5Bj6GVTKkQHFsWQH8olSzmiNerS+JuTKHFd5ttxOIwUUcD/Zvwf7oz0U8I9MHRS eD3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pw0bMx1GRPQBak2lHaVSU0d+3UNTn8TxVK9bJhryqWs=; b=jaf0oeqyeCRP0FfsTisCWOnc74cSX02sFWaBNr4PRqQFlrG6tZPLBiTUwKQwYZaxRQ l8c08Yrb/igd2FcCat0XH4N/UY058EdqNDGco2ww/EoxZ7g6y3zxBIDbc8uiitL2EFQf DRnhk/Vbg/+MiwGNPw4Hnb+xqzyJna2VAmucqSaQGclLefgT3SNijDf53U8KBksvQqJV xGLRp047n/Rsz88cyAHtv9+dIJ/OMZ1y4NWqcg5qoqCFF3drDS03gex/VD3FPdvWVfpl hDs1Rrr5ilN1BK9BeSdibCiKwtnGEU73Lo1RqLDVmX8NO/P+DHhteKpLaVVHJh4YUGdq YOSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PcWMSXMR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y14-20020aa79e0e000000b0064d5e97d4acsi3402021pfq.346.2023.06.03.21.57.50; Sat, 03 Jun 2023 21:58:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PcWMSXMR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbjFDE4B (ORCPT + 99 others); Sun, 4 Jun 2023 00:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230113AbjFDEz4 (ORCPT ); Sun, 4 Jun 2023 00:55:56 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B400DE; Sat, 3 Jun 2023 21:55:55 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3544tgLB057343; Sat, 3 Jun 2023 23:55:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685854542; bh=Pw0bMx1GRPQBak2lHaVSU0d+3UNTn8TxVK9bJhryqWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PcWMSXMRmmoTRoblXwHBE8AONQH/RCogK6HpNjWmDDvCdz1ir1tyEKPCcZpnlV/iW 3KQtv1Hp54rxWfE/i6Y6w/FdVdwYoNVThtMRx7RKteVQaO4EYajp5BWbrZhlH7sqHT u2RbPs0FuXydJVUNpo06R7VtXf1DUV5aQgd4Jg/U= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3544tgGl000617 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 3 Jun 2023 23:55:42 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 3 Jun 2023 23:55:42 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 3 Jun 2023 23:55:42 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3544tVqa052201; Sat, 3 Jun 2023 23:55:39 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar , Tony Lindgren Subject: [PATCH v3 2/5] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads Date: Sun, 4 Jun 2023 10:25:22 +0530 Message-ID: <20230604045525.1889083-3-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230604045525.1889083-1-u-kumar1@ti.com> References: <20230604045525.1889083-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767746761384575945?= X-GMAIL-MSGID: =?utf-8?q?1767746761384575945?= There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 +++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c6b15aceea82..a9b3bf8a5c6a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ cpts@3d000 { }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index dcb6696cff17..b518ec9eea32 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -183,6 +183,26 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */