diff mbox series

[13/21] clk: at91: sam9x7: add support for HW PLL freq dividers

Message ID 20230603200243.243878-14-varshini.rajendran@microchip.com
State New
Headers
Series Add support for sam9x7 SoC family |

Commit Message

Varshini Rajendran June 3, 2023, 8:02 p.m. UTC 
  Add support for hardware dividers for PLL IDs in sam9x7 Soc
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
 drivers/clk/at91/pmc.h             |  1 +
 2 files changed, 34 insertions(+), 5 deletions(-)

Comments

Claudiu Beznea June 15, 2023, 8 a.m. UTC | #1 
On 03.06.2023 23:02, Varshini Rajendran wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add support for hardware dividers for PLL IDs in sam9x7 Soc

dot at the end of line, probably.
s/Soc/SoC. Also, please explain it as clear as possible.

> PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each

At the time of this patch PLL_ID_PLLA and PLL_ID_PLLA_DIV2 does't exist
thus would be more clear if you reference datasheet naming.

Other than this code looks good to me.

Thank you,
Claudiu

> 
> fcorepllack -----> HW Div = 2 -+--> fpllack
>                                |
>                                +--> HW Div = 2 ---> fplladiv2ck
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
>  drivers/clk/at91/pmc.h             |  1 +
>  2 files changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b3012641214c..76273ea74f8b 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
>  {
>         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
>         struct sam9x60_frac *frac = to_sam9x60_frac(core);
> +       unsigned long freq;
> 
> -       return parent_rate * (frac->mul + 1) +
> +       freq = parent_rate * (frac->mul + 1) +
>                 DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> +       if (core->layout->div2)
> +               freq >>= 1;
> +
> +       return freq;
>  }
> 
>  static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
>         return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
>  }
> 
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> +                                                      unsigned long parent_rate)
> +{
> +       return parent_rate >> 1;
> +}
> +
>  static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
>                                         unsigned long *parent_rate,
>                                         unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
>         .restore_context = sam9x60_div_pll_restore_context,
>  };
> 
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> +       .prepare = sam9x60_div_pll_prepare,
> +       .unprepare = sam9x60_div_pll_unprepare,
> +       .is_prepared = sam9x60_div_pll_is_prepared,
> +       .recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> +       .round_rate = sam9x60_div_pll_round_rate,
> +       .save_context = sam9x60_div_pll_save_context,
> +       .restore_context = sam9x60_div_pll_restore_context,
> +};
> +
>  struct clk_hw * __init
>  sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>                               const char *name, const char *parent_name,
> @@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>         init.name = name;
>         init.parent_names = &parent_name;
>         init.num_parents = 1;
> -       if (flags & CLK_SET_RATE_GATE)
> -               init.ops = &sam9x60_div_pll_ops;
> -       else
> -               init.ops = &sam9x60_div_pll_ops_chg;
> +
> +       if (layout->div2) {
> +               init.ops = &sam9x60_fixed_div_pll_ops;
> +       } else {
> +               if (flags & CLK_SET_RATE_GATE)
> +                       init.ops = &sam9x60_div_pll_ops;
> +               else
> +                       init.ops = &sam9x60_div_pll_ops_chg;
> +       }
> +
>         init.flags = flags;
> 
>         div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 3e36dcc464c1..1dd01f30bdee 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
>         u8 frac_shift;
>         u8 div_shift;
>         u8 endiv_shift;
> +       u8 div2;
>  };
> 
>  extern const struct clk_pll_layout at91rm9200_pll_layout;
> --
> 2.25.1
> 
> 
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> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
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diff mbox series

Patch

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index b3012641214c..76273ea74f8b 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -73,9 +73,15 @@  static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 	struct sam9x60_frac *frac = to_sam9x60_frac(core);
+	unsigned long freq;
 
-	return parent_rate * (frac->mul + 1) +
+	freq = parent_rate * (frac->mul + 1) +
 		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
+
+	if (core->layout->div2)
+		freq >>= 1;
+
+	return freq;
 }
 
 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
@@ -432,6 +438,12 @@  static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 }
 
+static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
+						       unsigned long parent_rate)
+{
+	return parent_rate >> 1;
+}
+
 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 					unsigned long *parent_rate,
 					unsigned long rate)
@@ -606,6 +618,16 @@  static const struct clk_ops sam9x60_div_pll_ops_chg = {
 	.restore_context = sam9x60_div_pll_restore_context,
 };
 
+static const struct clk_ops sam9x60_fixed_div_pll_ops = {
+	.prepare = sam9x60_div_pll_prepare,
+	.unprepare = sam9x60_div_pll_unprepare,
+	.is_prepared = sam9x60_div_pll_is_prepared,
+	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
+	.round_rate = sam9x60_div_pll_round_rate,
+	.save_context = sam9x60_div_pll_save_context,
+	.restore_context = sam9x60_div_pll_restore_context,
+};
+
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
@@ -718,10 +740,16 @@  sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 	init.name = name;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
-	if (flags & CLK_SET_RATE_GATE)
-		init.ops = &sam9x60_div_pll_ops;
-	else
-		init.ops = &sam9x60_div_pll_ops_chg;
+
+	if (layout->div2) {
+		init.ops = &sam9x60_fixed_div_pll_ops;
+	} else {
+		if (flags & CLK_SET_RATE_GATE)
+			init.ops = &sam9x60_div_pll_ops;
+		else
+			init.ops = &sam9x60_div_pll_ops_chg;
+	}
+
 	init.flags = flags;
 
 	div->core.id = id;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 3e36dcc464c1..1dd01f30bdee 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -64,6 +64,7 @@  struct clk_pll_layout {
 	u8 frac_shift;
 	u8 div_shift;
 	u8 endiv_shift;
+	u8 div2;
 };
 
 extern const struct clk_pll_layout at91rm9200_pll_layout;