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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b62-20020a62cf41000000b0064d5cd354a7si697075pfg.82.2023.06.02.06.40.21; Fri, 02 Jun 2023 06:40:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=xLltTGXl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235321AbjFBNb7 (ORCPT + 99 others); Fri, 2 Jun 2023 09:31:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236252AbjFBNbt (ORCPT ); Fri, 2 Jun 2023 09:31:49 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C954E4C; Fri, 2 Jun 2023 06:31:26 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 352BikPi001501; Fri, 2 Jun 2023 15:31:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=SEnLjI1iAJ0BEpP1paBgUZKIcQgTv9KF2fDW8DrAk08=; b=xLltTGXldgai/457X8tQ4WXQ2qbQCiCK0w6103nkKKp34kBNl9chpQJcF1clZLoLTM/n +VpR3j8L7VVAftiQv51I+KX5rX1ON0Oua5p+YkezobTllzhMW8Yq6yJMoVsYLiP+mc6E rGlzwK2Zq61TxnNQCXBBsFMWxoc7nFJeP0c7Wk/QQou0FYtalPfpRYQwaw9cbwO6qXER XWXXOnyLPUMSGIAbaMH0U1hniqnpBIhwbjCeMWv/O54oufTLHEJaLU/qD0E4dQeNHeL3 oWy9IK78QTV0m1Ua/Oi6mk6rt4/ahKpqaSFSqTFNt5kmb8SQlJheOQDBPnSeGQNVpPLG KQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3qweqeph6a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 15:31:13 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1FC6610002A; Fri, 2 Jun 2023 15:31:13 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 17238236954; Fri, 2 Jun 2023 15:31:13 +0200 (CEST) Received: from localhost (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 2 Jun 2023 15:31:12 +0200 From: Alexandre Torgue To: , , Conor Dooley , Linus Walleij , Catalin Marinas , Will Deacon , Arnd Bergmann , Olof Johansson , CC: , , Alexandre Torgue , , , Subject: [PATCH v2 10/10] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE Date: Fri, 2 Jun 2023 15:28:59 +0200 Message-ID: <20230602132859.16442-11-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230602132859.16442-1-alexandre.torgue@foss.st.com> References: <20230602132859.16442-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-02_10,2023-06-02_02,2023-05-22_02 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767598440800621108?= X-GMAIL-MSGID: =?utf-8?q?1767598440800621108?= STM32 SoCs based on Armv8 have been added to the STM32 family. Those new SoCs are maintained as legacy STM32 MPU. Signed-off-by: Alexandre Torgue diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..06759396e220 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2849,6 +2849,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex F: arch/arm/boot/dts/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c +F: arch/arm64/boot/dts/st/ N: stm32 N: stm