Message ID | 20230602062552.565992-3-anshuman.khandual@arm.com |
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State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp828381vqr; Thu, 1 Jun 2023 23:27:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4pApveRdmFD5RP7kpnQO33HfnbEjFLFyq5WSaHFaLETCagkL7swHJuodyCXw1Dow0AOw+A X-Received: by 2002:a05:6a20:431b:b0:106:999f:64df with SMTP id h27-20020a056a20431b00b00106999f64dfmr13528563pzk.58.1685687274338; Thu, 01 Jun 2023 23:27:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685687274; cv=none; d=google.com; s=arc-20160816; b=BKrMkpdcu9JeVPcmohoB8SH+5BQ+BhOSMLi3OGIApAgc2og6gxk4CT4FkGTRMrGnW2 bsp8e7wVJo0bRaoAwK3Sgp1by9tCSyvv/EbcDnb360SENj6c33afXdT6Aq18Gjs+MgIu J7f9JkWFY3dYMBF+H/G8FSxW+Qc9ei4JwrPdgR6WJP5rLub4zIoHkTKOeTqwuT8qONCt GYo8oo8TodZs6dj75b6qxh/XucS/LGFQsMsPEwhv0YQBaw73Gkg4zhE1dwERBHtqgcYT SnUSLB7fo8cqok7xHBfm4x7s2O5SEGgmACpA/YAFuZXlR9QJXH+39Z4Maftp120R5N4V p6VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=z2/4qSXRE2q3Ba535MkTTdZxaIgUT+UNqWuh/xW0kpw=; b=nG0N0DWljIDPNJ1BVcSiYjIQB8eS8LNIQzDWZ32TNZ/PFlOhBeIOpthafG+jQvzZdg r+CiXBdFFVfEpljoESYrBHEn71AnuGfPX0S68M5C6mjsYeB5hiGrsC2y6nsw7PbfnyOd 3o4v6HexKWi1g6lGe9Wv85+XqJ9ANXVqD+/uMycV2PusBhZRoITeARXuqgItNYeKqVG/ UufYNeKmnlFcqIw4Qhk2MDWpIgLzyjCFzRx+kQQXZxmy9mIofQFo7brSdplC3MXaHQbp OiIXrcpuxaTeVrp899wvAXb1Dw7Xn87B/mWx0DDPN+flr0GFp7EGtMjCEvXQ5jEBRF4X KAXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w63-20020a638242000000b0053011490008si431427pgd.885.2023.06.01.23.27.41; Thu, 01 Jun 2023 23:27:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233766AbjFBG0S (ORCPT <rfc822;limurcpp@gmail.com> + 99 others); Fri, 2 Jun 2023 02:26:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233739AbjFBG0Q (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 2 Jun 2023 02:26:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 16242E7 for <linux-kernel@vger.kernel.org>; Thu, 1 Jun 2023 23:26:15 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45EA11474; Thu, 1 Jun 2023 23:27:00 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A2AB33F67D; Thu, 1 Jun 2023 23:26:10 -0700 (PDT) From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, broonie@kernel.org Cc: Anshuman Khandual <anshuman.khandual@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh@kernel.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, James Morse <james.morse@arm.com>, kvmarm@lists.linux.dev, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 02/14] arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools format Date: Fri, 2 Jun 2023 11:55:40 +0530 Message-Id: <20230602062552.565992-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602062552.565992-1-anshuman.khandual@arm.com> References: <20230602062552.565992-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767571219086449423?= X-GMAIL-MSGID: =?utf-8?q?1767571219086449423?= |
Series |
arm64/sysreg: Convert TRBE registers to automatic generation
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Commit Message
Anshuman Khandual
June 2, 2023, 6:25 a.m. UTC
This renames TRBPTR_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b2b67ae7525b..2cb1078bc67f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -254,8 +254,8 @@ #define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1) #define TRBLIMITR_EL1_FM_SHIFT 1 #define TRBLIMITR_EL1_E BIT(0) -#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) -#define TRBPTR_PTR_SHIFT 0 +#define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) +#define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) #define TRBBASER_BASE_SHIFT 12 #define TRBSR_EC_MASK GENMASK(5, 0)