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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org, broonie@kernel.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Rob Herring <robh@kernel.org>,
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James Morse <james.morse@arm.com>, kvmarm@lists.linux.dev,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: [PATCH V2 12/14] arm64/sysreg: Convert TRBMAR_EL1 register to
automatic generation
Date: Fri, 2 Jun 2023 11:55:50 +0530
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| Series |
arm64/sysreg: Convert TRBE registers to automatic generation
|
|
Commit Message
Anshuman Khandual
June 2, 2023, 6:25 a.m. UTC
This converts TRBMAR_EL1 register to automatic generation without
causing any functional change.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/sysreg.h | 5 -----
arch/arm64/tools/sysreg | 7 +++++++
2 files changed, 7 insertions(+), 5 deletions(-)
Comments
On Fri, Jun 02, 2023 at 11:55:50AM +0530, Anshuman Khandual wrote: > +Sysreg TRBMAR_EL1 3 0 9 11 4 > +Res0 63:12 > +Field 11:10 PAS > +Field 9:8 SH > +Field 7:0 Attr > +EndSysreg PAS and SH look like they should be enums, Attr is a bit more complex so Field is probably a good fit there. Adding the enum information could be done incrementally though so: Reviewed-by: Mark Brown <broonie@kernel.org>
On 6/2/23 17:35, Mark Brown wrote: > On Fri, Jun 02, 2023 at 11:55:50AM +0530, Anshuman Khandual wrote: > >> +Sysreg TRBMAR_EL1 3 0 9 11 4 >> +Res0 63:12 >> +Field 11:10 PAS >> +Field 9:8 SH >> +Field 7:0 Attr >> +EndSysreg > > PAS and SH look like they should be enums, Attr is a bit more complex so > Field is probably a good fit there. Adding the enum information could > be done incrementally though so: Will fold the following changes in this patch. --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2246,8 +2246,17 @@ EndSysreg Sysreg TRBMAR_EL1 3 0 9 11 4 Res0 63:12 -Field 11:10 PAS -Field 9:8 SH +Enum 11:10 PAS + 0b00 SECURE + 0b01 NON_SECURE + 0b10 ROOT + 0b11 REALM +EndEnum +Enum 9:8 SH + 0b00 NON_SHAREABLE + 0b10 OUTER_SHAREABLE + 0b11 INNER_SHAREABLE +EndEnum Field 7:0 Attr EndSysreg > > Reviewed-by: Mark Brown <broonie@kernel.org>
On Tue, Jun 13, 2023 at 09:31:13AM +0530, Anshuman Khandual wrote: > +Enum 11:10 PAS > + 0b00 SECURE > + 0b01 NON_SECURE > + 0b10 ROOT > + 0b11 REALM > +EndEnum > +Enum 9:8 SH > + 0b00 NON_SHAREABLE > + 0b10 OUTER_SHAREABLE > + 0b11 INNER_SHAREABLE > +EndEnum Sure.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 768d12fc4834..131442f850dd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,16 +235,11 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBMAR_EL1_SH_MASK GENMASK(9, 8) -#define TRBMAR_EL1_SH_SHIFT 8 -#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) -#define TRBMAR_EL1_Attr_SHIFT 0 #define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) #define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_EL1_F BIT(5) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6d12980f01c7..b3f9a545e1e7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2243,3 +2243,10 @@ Field 17 S Res0 16 Field 15:0 MSS EndSysreg + +Sysreg TRBMAR_EL1 3 0 9 11 4 +Res0 63:12 +Field 11:10 PAS +Field 9:8 SH +Field 7:0 Attr +EndSysreg