Message ID | 20230601142309.6307-3-guang.zeng@intel.com |
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State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m132-20020a633f8a000000b00541cfaad533si346818pga.88.2023.06.01.08.06.40; Thu, 01 Jun 2023 08:06:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eSNGS1F0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234153AbjFAPF6 (ORCPT <rfc822;limurcpp@gmail.com> + 99 others); Thu, 1 Jun 2023 11:05:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234933AbjFAPEv (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 1 Jun 2023 11:04:51 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE85FE7A; Thu, 1 Jun 2023 08:03:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685631817; x=1717167817; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=kZ/mbZNr5jyMMC2Stb6kF5aPD2uJleqw++i6qKuFJOM=; b=eSNGS1F09TPtjl5GIWIAAReBSwjX443gFqeA2hhJF4wfOKcPYsvnZoD4 o8vSM21iBQ2rRu28tzPcf9rT1MWZyeQc6CZuJukMp8ATSLOW0lKGMdnAS Bx1NvaKiSwCCha7/FH9mdg5BNRlvQZUNA4uSl+8a1wMdUh5VkCkpz+Bps WWltyIGeF9ONobL6FMFE+Uhb0XiT+SXVcYAxznUjvt+34dK7i8bxVt1ZO 8MR5GRkRsSl7audL+uWSVkGMNq96MnQvzlQ7JZEl884c6zMnaLkbQO99L AkT2JFr7D27GbkunjQPKVV+ssTmzK7hytKQ0DPCh0tT7H9viiTV+JA+45 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10728"; a="383853377" X-IronPort-AV: E=Sophos;i="6.00,210,1681196400"; d="scan'208";a="383853377" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2023 08:02:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10728"; a="657828187" X-IronPort-AV: E=Sophos;i="6.00,210,1681196400"; d="scan'208";a="657828187" Received: from arthur-vostro-3668.sh.intel.com ([10.238.200.123]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2023 08:02:42 -0700 From: Zeng Guang <guang.zeng@intel.com> To: Paolo Bonzini <pbonzini@redhat.com>, Sean Christopherson <seanjc@google.com>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Dave Hansen <dave.hansen@linux.intel.com>, H Peter Anvin <hpa@zytor.com>, kvm@vger.kernel.org Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Zeng Guang <guang.zeng@intel.com> Subject: [PATCH v1 2/6] KVM: x86: Virtualize CR4.LASS Date: Thu, 1 Jun 2023 22:23:05 +0800 Message-Id: <20230601142309.6307-3-guang.zeng@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230601142309.6307-1-guang.zeng@intel.com> References: <20230601142309.6307-1-guang.zeng@intel.com> X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767513279664153999?= X-GMAIL-MSGID: =?utf-8?q?1767513279664153999?= |
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LASS KVM virtualization support
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Commit Message
Zeng Guang
June 1, 2023, 2:23 p.m. UTC
Virtualize CR4.LASS[bit 27] under KVM control instead of being guest-owned as CR4.LASS generally set once for each vCPU at boot time and won't be toggled at runtime. Besides, only if VM has LASS capability enumerated with CPUID.(EAX=07H.ECX=1):EAX.LASS[bit 6], KVM allows guest software to be able to set CR4.LASS. Updating cr4_fixed1 to set CR4.LASS bit in the emulated IA32_VMX_CR4_FIXED1 MSR for guests and allow guests to enable LASS in nested VMX operaion as well. Notes: Setting CR4.LASS to 1 enable LASS in IA-32e mode. It doesn't take effect in legacy mode even if CR4.LASS is set. Signed-off-by: Zeng Guang <guang.zeng@intel.com> Tested-by: Xuelian Guo <xuelian.guo@intel.com> --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/vmx.c | 3 +++ arch/x86/kvm/x86.h | 2 ++ 3 files changed, 6 insertions(+), 1 deletion(-)
Comments
On 6/1/2023 10:23 PM, Zeng Guang wrote: > Virtualize CR4.LASS[bit 27] under KVM control instead of being guest-owned > as CR4.LASS generally set once for each vCPU at boot time and won't be > toggled at runtime. Besides, only if VM has LASS capability enumerated with > CPUID.(EAX=07H.ECX=1):EAX.LASS[bit 6], KVM allows guest software to be able > to set CR4.LASS. > > Updating cr4_fixed1 to set CR4.LASS bit in the emulated IA32_VMX_CR4_FIXED1 > MSR for guests and allow guests to enable LASS in nested VMX operaion as well. s/operaion/operation > > Notes: Setting CR4.LASS to 1 enable LASS in IA-32e mode. It doesn't take > effect in legacy mode even if CR4.LASS is set. > > Signed-off-by: Zeng Guang <guang.zeng@intel.com> > Tested-by: Xuelian Guo <xuelian.guo@intel.com> > --- > arch/x86/include/asm/kvm_host.h | 2 +- > arch/x86/kvm/vmx/vmx.c | 3 +++ > arch/x86/kvm/x86.h | 2 ++ > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index fb9d1f2d6136..92d8e65fe88c 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -125,7 +125,7 @@ > | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ > | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ > | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ > - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) > + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP | X86_CR4_LASS)) Suppose there is some bare-matel linux patch to define the LASS related macros. May be better to describe the dependent patch(es) in cover letter. > > #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 44fb619803b8..a33205ded85c 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -7603,6 +7603,9 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) > cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); > cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); > > + entry = kvm_find_cpuid_entry_index(vcpu, 0x7, 1); > + cr4_fixed1_update(X86_CR4_LASS, eax, feature_bit(LASS)); > + > #undef cr4_fixed1_update > } > > diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h > index c544602d07a3..e1295f490308 100644 > --- a/arch/x86/kvm/x86.h > +++ b/arch/x86/kvm/x86.h > @@ -529,6 +529,8 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); > __reserved_bits |= X86_CR4_VMXE; \ > if (!__cpu_has(__c, X86_FEATURE_PCID)) \ > __reserved_bits |= X86_CR4_PCIDE; \ > + if (!__cpu_has(__c, X86_FEATURE_LASS)) \ > + __reserved_bits |= X86_CR4_LASS; \ > __reserved_bits; \ > }) >
On 6/5/2023 9:57 AM, Binbin Wu wrote: > > On 6/1/2023 10:23 PM, Zeng Guang wrote: >> Virtualize CR4.LASS[bit 27] under KVM control instead of being guest-owned >> as CR4.LASS generally set once for each vCPU at boot time and won't be >> toggled at runtime. Besides, only if VM has LASS capability enumerated with >> CPUID.(EAX=07H.ECX=1):EAX.LASS[bit 6], KVM allows guest software to be able >> to set CR4.LASS. >> >> Updating cr4_fixed1 to set CR4.LASS bit in the emulated IA32_VMX_CR4_FIXED1 >> MSR for guests and allow guests to enable LASS in nested VMX operaion as well. > s/operaion/operation Thanks. > >> Notes: Setting CR4.LASS to 1 enable LASS in IA-32e mode. It doesn't take >> effect in legacy mode even if CR4.LASS is set. >> >> Signed-off-by: Zeng Guang <guang.zeng@intel.com> >> Tested-by: Xuelian Guo <xuelian.guo@intel.com> >> --- >> arch/x86/include/asm/kvm_host.h | 2 +- >> arch/x86/kvm/vmx/vmx.c | 3 +++ >> arch/x86/kvm/x86.h | 2 ++ >> 3 files changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h >> index fb9d1f2d6136..92d8e65fe88c 100644 >> --- a/arch/x86/include/asm/kvm_host.h >> +++ b/arch/x86/include/asm/kvm_host.h >> @@ -125,7 +125,7 @@ >> | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ >> | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ >> | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ >> - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) >> + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP | X86_CR4_LASS)) > Suppose there is some bare-matel linux patch to define the LASS related > macros. > May be better to describe the dependent patch(es) in cover letter. > Good suggestion.
On Thu, Jun 01, 2023, Zeng Guang wrote: > Virtualize CR4.LASS[bit 27] under KVM control instead of being guest-owned > as CR4.LASS generally set once for each vCPU at boot time and won't be > toggled at runtime. Besides, only if VM has LASS capability enumerated with > CPUID.(EAX=07H.ECX=1):EAX.LASS[bit 6], KVM allows guest software to be able > to set CR4.LASS. > > Updating cr4_fixed1 to set CR4.LASS bit in the emulated IA32_VMX_CR4_FIXED1 > MSR for guests and allow guests to enable LASS in nested VMX operaion as well. s/operaion/operation.
On 6/28/2023 1:43 AM, Sean Christopherson wrote: > On Thu, Jun 01, 2023, Zeng Guang wrote: >> Virtualize CR4.LASS[bit 27] under KVM control instead of being guest-owned >> as CR4.LASS generally set once for each vCPU at boot time and won't be >> toggled at runtime. Besides, only if VM has LASS capability enumerated with >> CPUID.(EAX=07H.ECX=1):EAX.LASS[bit 6], KVM allows guest software to be able >> to set CR4.LASS. >> >> Updating cr4_fixed1 to set CR4.LASS bit in the emulated IA32_VMX_CR4_FIXED1 >> MSR for guests and allow guests to enable LASS in nested VMX operaion as well. > s/operaion/operation. Will fix in next version. Thanks.
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index fb9d1f2d6136..92d8e65fe88c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -125,7 +125,7 @@ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP | X86_CR4_LASS)) #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 44fb619803b8..a33205ded85c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7603,6 +7603,9 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); + entry = kvm_find_cpuid_entry_index(vcpu, 0x7, 1); + cr4_fixed1_update(X86_CR4_LASS, eax, feature_bit(LASS)); + #undef cr4_fixed1_update } diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index c544602d07a3..e1295f490308 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -529,6 +529,8 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); __reserved_bits |= X86_CR4_VMXE; \ if (!__cpu_has(__c, X86_FEATURE_PCID)) \ __reserved_bits |= X86_CR4_PCIDE; \ + if (!__cpu_has(__c, X86_FEATURE_LASS)) \ + __reserved_bits |= X86_CR4_LASS; \ __reserved_bits; \ })