Message ID | 20230601065805.18079-4-quic_kbajaj@quicinc.com |
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Thu, 01 Jun 2023 06:58:15 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3516wBNv022073; Thu, 1 Jun 2023 06:58:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3quaxm7e8g-1; Thu, 01 Jun 2023 06:58:11 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3516wALH022057; Thu, 1 Jun 2023 06:58:11 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3516wAuu022055; Thu, 01 Jun 2023 06:58:11 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 5F1D2529757; Thu, 1 Jun 2023 12:28:10 +0530 (+0530) From: Komal Bajaj <quic_kbajaj@quicinc.com> To: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Bhupesh Sharma <bhupesh.sharma@linaro.org> Cc: Komal Bajaj <quic_kbajaj@quicinc.com>, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v4 3/4] arm64: dts: qcom: qdu1000: Add SDHCI pin configuration to DTSI Date: Thu, 1 Jun 2023 12:28:04 +0530 Message-Id: <20230601065805.18079-4-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230601065805.18079-1-quic_kbajaj@quicinc.com> References: <20230601065805.18079-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MtvXlEds4_bP_cZ1-hRN0X2eu9bdP0GW X-Proofpoint-ORIG-GUID: MtvXlEds4_bP_cZ1-hRN0X2eu9bdP0GW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_04,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxlogscore=640 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010061 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767482938149266122?= X-GMAIL-MSGID: =?utf-8?q?1767483152928894771?= |
Series |
arm64: dts: qcom: qdu1000: add SDHCI
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Commit Message
Komal Bajaj
June 1, 2023, 6:58 a.m. UTC
Add required pins for SDHCI, so that the interface can work reliably.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 50 +++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
--
2.17.1
Comments
On 1.06.2023 08:58, Komal Bajaj wrote: > Add required pins for SDHCI, so that the interface can work reliably. > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 50 +++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > index 6df07334f1d3..9f615f3368c2 100644 > --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -1147,6 +1147,56 @@ > pins = "gpio31"; > function = "gpio"; > }; > + > + sdc_on_state: sdc-on-state { > + clk-pins { > + pins = "sdc1_clk"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc_off_state: sdc-off-state { > + clk-pins { > + pins = "sdc1_clk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > }; > > apps_smmu: iommu@15000000 { > -- > 2.17.1 >
On 1.06.2023 09:00, Krzysztof Kozlowski wrote: > On 01/06/2023 08:58, Komal Bajaj wrote: >> Add required pins for SDHCI, so that the interface can work reliably. >> > > This is not a separate commit. The pin configuration by itself does not > make sense and we don't need it. It's part of adding SDHCI, so squash it. keep my rb for the squashed patch Konrad > > Best regards, > Krzysztof >
On 6/1/2023 12:30 PM, Krzysztof Kozlowski wrote: > On 01/06/2023 08:58, Komal Bajaj wrote: >> Add required pins for SDHCI, so that the interface can work reliably. >> > This is not a separate commit. The pin configuration by itself does not > make sense and we don't need it. It's part of adding SDHCI, so squash it. Okay, will combine this patch with 2nd in the next patch series. Thanks Komal > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 6df07334f1d3..9f615f3368c2 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1147,6 +1147,56 @@ pins = "gpio31"; function = "gpio"; }; + + sdc_on_state: sdc-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc_off_state: sdc-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; }; apps_smmu: iommu@15000000 {