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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id v3-20020a056512048300b004f3b258feefsm1031119lfq.179.2023.06.01.02.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 02:39:12 -0700 (PDT) From: Konrad Dybcio Date: Thu, 01 Jun 2023 11:39:07 +0200 Subject: [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) MIME-Version: 1.0 Message-Id: <20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org> References: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org> In-Reply-To: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Iskren Chernev Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685612350; l=2006; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wYVC8kdHJdhvnMuMnLKibz47EG2aGZVDSm2mijcxJhM=; b=H/wQbdL0OfMcmYF31Muucv9e8Y7m1Ku/adaUr5wH7HSFZoLNywx+S3xNliNCQmZmE65dFR5at ocJiQSpxaKuAZx85XvQwtUbafzOoFp3gs9IprHtdFk9jb61DJK6kTHD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767493628317270170?= X-GMAIL-MSGID: =?utf-8?q?1767493628317270170?= The "vanilla" Alpha PLL configs are sometimes provided with an intention to only update certain bits of th register. Do so if a mask is found. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++---- drivers/clk/qcom/clk-alpha-pll.h | 2 ++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f81c7c561352..e4ef645f65d1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -384,10 +384,21 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); - clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), - config->test_ctl_val); - clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), - config->test_ctl_hi_val); + if (config->test_ctl_mask) + regmap_update_bits(regmap, PLL_TEST_CTL(pll), + config->test_ctl_mask, + config->test_ctl_val); + else + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), + config->test_ctl_val); + + if (config->test_ctl_hi_mask) + regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_mask, + config->test_ctl_hi_val); + else + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_val); if (pll->flags & SUPPORTS_FSM_MODE) qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6ff0d08eb938..e4bd863027ab 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -123,7 +123,9 @@ struct alpha_pll_config { u32 user_ctl_hi_val; u32 user_ctl_hi1_val; u32 test_ctl_val; + u32 test_ctl_mask; u32 test_ctl_hi_val; + u32 test_ctl_hi_mask; u32 test_ctl_hi1_val; u32 test_ctl_hi2_val; u32 main_output_mask;